Get rid of 3 of the 4 'printimplicit' flags. Implicit operands are now

[oota-llvm.git] / lib / CodeGen / InstrSched / InstrScheduling.cpp

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 403243224720ceff569d989cf636386ba91585aa..240bdefe94e72fdd263db4868a1b0333d33ca6c7 100644 (file)
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -16,11 +16,12 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/FunctionLiveVarInfo.h"
+#include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/BasicBlock.h"
 #include "Support/CommandLine.h"
 #include <algorithm>
+#include <iostream>
 
 namespace llvm {
 
@@ -37,7 +38,7 @@ SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
  clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
  clEnumValN(Sched_PrintSchedTrace,  "t", "print trace of scheduling actions"),
  clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"),
-                   0));
+                   clEnumValEnd));
 
 
 //************************* Internal Data Types *****************************/
@@ -192,7 +193,10 @@ public: // accessor functions to query chosen schedule
                                         unsigned int slotNum,
                                         cycles_t cycle) {
     InstrGroup* igroup = this->getIGroup(cycle);
-    assert((*igroup)[slotNum] == NULL &&  "Slot already filled?");
+    if (!((*igroup)[slotNum] == NULL)) {
+      std::cerr << "Slot already filled?\n";
+      abort();
+    }
     igroup->addInstr(node, slotNum);
     assert(node->getNodeId() < startTime.size());
     startTime[node->getNodeId()] = cycle;
@@ -512,15 +516,15 @@ private:
 SchedulingManager::SchedulingManager(const TargetMachine& target,
                                     const SchedGraph* graph,
                                     SchedPriorities& _schedPrio)
-  : nslots(target.getSchedInfo().getMaxNumIssueTotal()),
-    schedInfo(target.getSchedInfo()),
+  : nslots(target.getSchedInfo()->getMaxNumIssueTotal()),
+    schedInfo(*target.getSchedInfo()),
     schedPrio(_schedPrio),
     isched(nslots, graph->getNumNodes()),
     totalInstrCount(graph->getNumNodes() - 2),
     nextEarliestIssueTime(0),
     choicesForSlot(nslots),
-    numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
-    nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
+    numInClass(target.getSchedInfo()->getNumSchedClasses(), 0),        // set all to 0
+    nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(),
                          (cycles_t) 0)                         // set all to 0
 {
   updateTime(0);
@@ -625,7 +629,6 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
 {
   const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
   
-#ifndef NDEBUG
   // Lets make sure we didn't lose any instructions, except possibly
   // some NOPs from delay slots.  Also, PHIs are not included in the schedule.
   unsigned numInstr = 0;
@@ -635,7 +638,6 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
       ++numInstr;
   assert(S.isched.getNumInstructions() >= numInstr &&
         "Lost some non-NOP instructions during scheduling!");
-#endif
   
   if (S.isched.getNumInstructions() == 0)
     return;                            // empty basic block!
@@ -648,7 +650,8 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   
   // Remove all except the dummy PHI instructions from MBB, and
   // pre-allocate create space for the ones we will put back in.
-  while (I != MBB.end()) MBB.remove(I);
+  while (I != MBB.end())
+    MBB.remove(I++);
   
   InstrSchedule::const_iterator NIend = S.isched.end();
   for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
@@ -1043,11 +1046,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
        && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
       return false;
   
-  // for now, don't put an instruction that does not have operand
-  // interlocks in the delay slot of a branch
-  if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
-    return false;
-  
   // Finally, if the instruction precedes the branch, we make sure the
   // instruction can be reordered relative to the branch.  We simply check
   // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
@@ -1177,8 +1175,10 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
   MachineBasicBlock& MBB = node->getMachineBasicBlock();
   MachineBasicBlock::iterator MBBI = MBB.begin();
   std::advance(MBBI, firstDelaySlotIdx - 1);
-  assert(&*MBBI++ == brInstr &&
-         "Incorrect instr. index in basic block for brInstr");
+  if (!(&*MBBI++ == brInstr)) {
+    std::cerr << "Incorrect instr. index in basic block for brInstr";
+    abort();
+  }
   
   // First find all useful instructions already in the delay slots
   // and USE THEM.  We'll throw away the unused alternatives below
@@ -1324,11 +1324,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
       const SchedGraphNode* dnode = delayNodeVec[i];
       if ( ! S.isScheduled(dnode)
            && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
-           && instrIsFeasible(S, dnode->getOpcode()))
-      {
-        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
-               && "Instructions without interlocks not yet supported "
-               "when filling branch delay slots");
+           && instrIsFeasible(S, dnode->getOpcode())) {
         S.scheduleInstr(dnode, nextSlot, nextTime);
         break;
       }