-// $Id$ -*-c++-*-
-//***************************************************************************
-// File:
-// InstrSelectionSupport.h
+//===-- InstrSelectionSupport.cpp -----------------------------------------===//
+//
+// Target-independent instruction selection code. See SparcInstrSelection.cpp
+// for usage.
//
-// Purpose:
-// Target-independent instruction selection code.
-// See SparcInstrSelection.cpp for usage.
-//
-// History:
-// 10/10/01 - Vikram Adve - Created
-//**************************************************************************/
+//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/InstrSelection.h"
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrAnnot.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineRegInfo.h"
-#include "llvm/ConstPoolVals.h"
-#include "llvm/Instruction.h"
-#include "llvm/Type.h"
-#include "llvm/iMemory.h"
-
+#include "llvm/Target/TargetRegInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Constants.h"
+#include "llvm/BasicBlock.h"
+#include "llvm/DerivedTypes.h"
+using std::vector;
//*************************** Local Functions ******************************/
-inline int64_t
-GetSignedIntConstantValue(Value* val, bool& isValidConstant)
-{
- int64_t intValue = 0;
- isValidConstant = false;
-
- if (val->getValueType() == Value::ConstantVal)
- {
- switch(val->getType()->getPrimitiveID())
- {
- case Type::BoolTyID:
- intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
- isValidConstant = true;
- break;
- case Type::SByteTyID:
- case Type::ShortTyID:
- case Type::IntTyID:
- case Type::LongTyID:
- intValue = ((ConstPoolSInt*) val)->getValue();
- isValidConstant = true;
- break;
- default:
- break;
- }
- }
-
- return intValue;
-}
-inline uint64_t
-GetUnsignedIntConstantValue(Value* val, bool& isValidConstant)
-{
- uint64_t intValue = 0;
- isValidConstant = false;
-
- if (val->getValueType() == Value::ConstantVal)
- {
- switch(val->getType()->getPrimitiveID())
- {
- case Type::BoolTyID:
- intValue = ((ConstPoolBool*) val)->getValue()? 1 : 0;
- isValidConstant = true;
- break;
- case Type::UByteTyID:
- case Type::UShortTyID:
- case Type::UIntTyID:
- case Type::ULongTyID:
- intValue = ((ConstPoolUInt*) val)->getValue();
- isValidConstant = true;
- break;
- default:
- break;
- }
- }
-
- return intValue;
-}
-
-
-inline int64_t
-GetConstantValueAsSignedInt(Value* val, bool& isValidConstant)
-{
- int64_t intValue = 0;
-
- if (val->getType()->isSigned())
- {
- intValue = GetSignedIntConstantValue(val, isValidConstant);
- }
- else // non-numeric types will fall here
- {
- uint64_t uintValue = GetUnsignedIntConstantValue(val, isValidConstant);
- if (isValidConstant && uintValue < INT64_MAX) // safe to use signed
- intValue = (int64_t) uintValue;
- else
- isValidConstant = false;
- }
-
- return intValue;
-}
-
-
-//---------------------------------------------------------------------------
-// Function: FoldGetElemChain
+// Generate code to load the constant into a TmpInstruction (virtual reg) and
+// returns the virtual register.
//
-// Purpose:
-// Fold a chain of GetElementPtr instructions into an equivalent
-// (Pointer, IndexVector) pair. Returns the pointer Value, and
-// stores the resulting IndexVector in argument chainIdxVec.
-//---------------------------------------------------------------------------
-
-Value*
-FoldGetElemChain(const InstructionNode* getElemInstrNode,
- vector<ConstPoolVal*>& chainIdxVec)
+static TmpInstruction*
+InsertCodeToLoadConstant(Function *F,
+ Value* opValue,
+ Instruction* vmInstr,
+ vector<MachineInstr*>& loadConstVec,
+ TargetMachine& target)
{
- MemAccessInst* getElemInst = (MemAccessInst*)
- getElemInstrNode->getInstruction();
+ // Create a tmp virtual register to hold the constant.
+ TmpInstruction* tmpReg = new TmpInstruction(opValue);
+ MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
+ mcfi.addTemp(tmpReg);
- // Initialize return values from the incoming instruction
- Value* ptrVal = getElemInst->getPtrOperand();
- chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
+ target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
+ loadConstVec, mcfi);
- // Now chase the chain of getElementInstr instructions, if any
- InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
- while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
- ptrChild->getOpLabel() == GetElemPtrIdx)
- {
- // Child is a GetElemPtr instruction
- getElemInst = (MemAccessInst*)
- ((InstructionNode*) ptrChild)->getInstruction();
- const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
-
- // Get the pointer value out of ptrChild and *prepend* its index vector
- ptrVal = getElemInst->getPtrOperand();
- chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
-
- ptrChild = ptrChild->leftChild();
- }
+ // Record the mapping from the tmp VM instruction to machine instruction.
+ // Do this for all machine instructions that were not mapped to any
+ // other temp values created by
+ // tmpReg->addMachineInstruction(loadConstVec.back());
- return ptrVal;
+ return tmpReg;
}
-//------------------------------------------------------------------------
-// Function Set2OperandsFromInstr
-// Function Set3OperandsFromInstr
-//
-// For the common case of 2- and 3-operand arithmetic/logical instructions,
-// set the m/c instr. operands directly from the VM instruction's operands.
-// Check whether the first or second operand is 0 and can use a dedicated "0"
-// register.
-// Check whether the second operand should use an immediate field or register.
-// (First and third operands are never immediates for such instructions.)
-//
-// Arguments:
-// canDiscardResult: Specifies that the result operand can be discarded
-// by using the dedicated "0"
-//
-// op1position, op2position and resultPosition: Specify in which position
-// in the machine instruction the 3 operands (arg1, arg2
-// and result) should go.
-//
-// RETURN VALUE: unsigned int flags, where
-// flags & 0x01 => operand 1 is constant and needs a register
-// flags & 0x02 => operand 2 is constant and needs a register
-//------------------------------------------------------------------------
-
-void
-Set2OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& target,
- bool canDiscardResult,
- int op1Position,
- int resultPosition)
+MachineOperand::MachineOperandType
+ChooseRegOrImmed(int64_t intValue,
+ bool isSigned,
+ MachineOpCode opCode,
+ const TargetMachine& target,
+ bool canUseImmed,
+ unsigned int& getMachineRegNum,
+ int64_t& getImmedValue)
{
- Set3OperandsFromInstr(minstr, vmInstrNode, target,
- canDiscardResult, op1Position,
- /*op2Position*/ -1, resultPosition);
-}
+ MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
+ getMachineRegNum = 0;
+ getImmedValue = 0;
-#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
-#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
-unsigned
-Set3OperandsFromInstrJUNK(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& target,
- bool canDiscardResult,
- int op1Position,
- int op2Position,
- int resultPosition)
-{
- assert(op1Position >= 0);
- assert(resultPosition >= 0);
-
- unsigned returnFlags = 0x0;
-
- // Check if operand 1 is 0. If so, try to use a hardwired 0 register.
- Value* op1Value = vmInstrNode->leftChild()->getValue();
- bool isValidConstant;
- int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
- if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
- minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
- else
+ if (canUseImmed &&
+ target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
{
- if (isa<ConstPoolVal>(op1Value))
- {
- // value is constant and must be loaded from constant pool
- returnFlags = returnFlags | (1 << op1Position);
- }
- minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
- op1Value);
+ opType = isSigned? MachineOperand::MO_SignExtendedImmed
+ : MachineOperand::MO_UnextendedImmed;
+ getImmedValue = intValue;
}
-
- // Check if operand 2 (if any) fits in the immed. field of the instruction,
- // or if it is 0 and can use a dedicated machine register
- if (op2Position >= 0)
+ else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
{
- Value* op2Value = vmInstrNode->rightChild()->getValue();
- int64_t immedValue;
- unsigned int machineRegNum;
-
- MachineOperand::MachineOperandType
- op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
- /*canUseImmed*/ true,
- machineRegNum, immedValue);
-
- if (op2type == MachineOperand::MO_MachineRegister)
- minstr->SetMachineOperand(op2Position, machineRegNum);
- else if (op2type == MachineOperand::MO_VirtualRegister)
- {
- if (isa<ConstPoolVal>(op2Value))
- {
- // value is constant and must be loaded from constant pool
- returnFlags = returnFlags | (1 << op2Position);
- }
- minstr->SetMachineOperand(op2Position, op2type, op2Value);
- }
- else
- {
- assert(op2type != MO_CCRegister);
- minstr->SetMachineOperand(op2Position, op2type, immedValue);
- }
+ opType = MachineOperand::MO_MachineRegister;
+ getMachineRegNum = target.getRegInfo().getZeroRegNum();
}
-
- // If operand 3 (result) can be discarded, use a dead register if one exists
- if (canDiscardResult && target.zeroRegNum >= 0)
- minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
- else
- minstr->SetMachineOperand(resultPosition,
- MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
-
- return returnFlags;
-}
-#endif
-
-void
-Set3OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& target,
- bool canDiscardResult,
- int op1Position,
- int op2Position,
- int resultPosition)
-{
- assert(op1Position >= 0);
- assert(resultPosition >= 0);
-
- // operand 1
- minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
- vmInstrNode->leftChild()->getValue());
-
- // operand 2 (if any)
- if (op2Position >= 0)
- minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
- vmInstrNode->rightChild()->getValue());
-
- // result operand: if it can be discarded, use a dead register if one exists
- if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
- minstr->SetMachineOperand(resultPosition,
- target.getRegInfo().getZeroRegNum());
- else
- minstr->SetMachineOperand(resultPosition,
- MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
+ return opType;
}
unsigned int& getMachineRegNum,
int64_t& getImmedValue)
{
- MachineOperand::MachineOperandType opType =
- MachineOperand::MO_VirtualRegister;
getMachineRegNum = 0;
getImmedValue = 0;
-
- // Check for the common case first: argument is not constant
- //
- ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
- if (!CPV) return opType;
- if (CPV->getType() == Type::BoolTy)
- {
- ConstPoolBool *CPB = (ConstPoolBool*)CPV;
- if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
- {
- getMachineRegNum = target.getRegInfo().getZeroRegNum();
- return MachineOperand::MO_MachineRegister;
- }
-
- getImmedValue = 1;
- return MachineOperand::MO_SignExtendedImmed;
- }
-
- if (!CPV->getType()->isIntegral()) return opType;
+ // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
+ Constant *CPV = dyn_cast<Constant>(val);
+ if (CPV == NULL ||
+ (! CPV->getType()->isIntegral() &&
+ ! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
+ return MachineOperand::MO_VirtualRegister;
// Now get the constant value and check if it fits in the IMMED field.
// Take advantage of the fact that the max unsigned value will rarely
// unsigned constants to signed).
//
int64_t intValue;
- if (CPV->getType()->isSigned())
- {
- intValue = ((ConstPoolSInt*)CPV)->getValue();
- }
+ if (isa<PointerType>(CPV->getType()))
+ intValue = 0; // We checked above that it is NULL
+ else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
+ intValue = (int64_t) CB->getValue();
+ else if (CPV->getType()->isSigned())
+ intValue = cast<ConstantSInt>(CPV)->getValue();
else
- {
- uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
- if (V >= INT64_MAX) return opType;
- intValue = (int64_t)V;
+ { // get the int value and sign-extend if original was less than 64 bits
+ intValue = (int64_t) cast<ConstantUInt>(CPV)->getValue();
+ switch(CPV->getType()->getPrimitiveID())
+ {
+ case Type::UByteTyID: intValue = (int64_t) (int8_t) intValue; break;
+ case Type::UShortTyID: intValue = (int64_t) (short) intValue; break;
+ case Type::UIntTyID: intValue = (int64_t) (int) intValue; break;
+ default: break;
+ }
}
- if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
- {
- opType = MachineOperand::MO_MachineRegister;
- getMachineRegNum = target.getRegInfo().getZeroRegNum();
- }
- else if (canUseImmed &&
- target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
+ return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
+ opCode, target, canUseImmed,
+ getMachineRegNum, getImmedValue);
+}
+
+
+
+//---------------------------------------------------------------------------
+// Function: FixConstantOperandsForInstr
+//
+// Purpose:
+// Special handling for constant operands of a machine instruction
+// -- if the constant is 0, use the hardwired 0 register, if any;
+// -- if the constant fits in the IMMEDIATE field, use that field;
+// -- else create instructions to put the constant into a register, either
+// directly or by loading explicitly from the constant pool.
+//
+// In the first 2 cases, the operand of `minstr' is modified in place.
+// Returns a vector of machine instructions generated for operands that
+// fall under case 3; these must be inserted before `minstr'.
+//---------------------------------------------------------------------------
+
+vector<MachineInstr*>
+FixConstantOperandsForInstr(Instruction* vmInstr,
+ MachineInstr* minstr,
+ TargetMachine& target)
+{
+ vector<MachineInstr*> MVec;
+
+ MachineOpCode opCode = minstr->getOpCode();
+ const TargetInstrInfo& instrInfo = target.getInstrInfo();
+ int resultPos = instrInfo.getResultPos(opCode);
+ int immedPos = instrInfo.getImmedConstantPos(opCode);
+
+ Function *F = vmInstr->getParent()->getParent();
+
+ for (unsigned op=0; op < minstr->getNumOperands(); op++)
{
- opType = MachineOperand::MO_SignExtendedImmed;
- getImmedValue = intValue;
+ const MachineOperand& mop = minstr->getOperand(op);
+
+ // Skip the result position, preallocated machine registers, or operands
+ // that cannot be constants (CC regs or PC-relative displacements)
+ if (resultPos == (int)op ||
+ mop.getType() == MachineOperand::MO_MachineRegister ||
+ mop.getType() == MachineOperand::MO_CCRegister ||
+ mop.getType() == MachineOperand::MO_PCRelativeDisp)
+ continue;
+
+ bool constantThatMustBeLoaded = false;
+ unsigned int machineRegNum = 0;
+ int64_t immedValue = 0;
+ Value* opValue = NULL;
+ MachineOperand::MachineOperandType opType =
+ MachineOperand::MO_VirtualRegister;
+
+ // Operand may be a virtual register or a compile-time constant
+ if (mop.getType() == MachineOperand::MO_VirtualRegister)
+ {
+ assert(mop.getVRegValue() != NULL);
+ opValue = mop.getVRegValue();
+ if (Constant *opConst = dyn_cast<Constant>(opValue)) {
+ opType = ChooseRegOrImmed(opConst, opCode, target,
+ (immedPos == (int)op), machineRegNum,
+ immedValue);
+ if (opType == MachineOperand::MO_VirtualRegister)
+ constantThatMustBeLoaded = true;
+ }
+ }
+ else
+ {
+ assert(mop.isImmediate());
+ bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
+
+ // Bit-selection flags indicate an instruction that is extracting
+ // bits from its operand so ignore this even if it is a big constant.
+ if (mop.opHiBits32() || mop.opLoBits32() ||
+ mop.opHiBits64() || mop.opLoBits64())
+ continue;
+
+ opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
+ opCode, target, (immedPos == (int)op),
+ machineRegNum, immedValue);
+
+ if (opType == mop.getType())
+ continue; // no change: this is the most common case
+
+ if (opType == MachineOperand::MO_VirtualRegister)
+ {
+ constantThatMustBeLoaded = true;
+ opValue = isSigned
+ ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
+ : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
+ }
+ }
+
+ if (opType == MachineOperand::MO_MachineRegister)
+ minstr->SetMachineOperandReg(op, machineRegNum);
+ else if (opType == MachineOperand::MO_SignExtendedImmed ||
+ opType == MachineOperand::MO_UnextendedImmed)
+ minstr->SetMachineOperandConst(op, opType, immedValue);
+ else if (constantThatMustBeLoaded ||
+ (opValue && isa<GlobalValue>(opValue)))
+ { // opValue is a constant that must be explicitly loaded into a reg
+ assert(opValue);
+ TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
+ MVec, target);
+ minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
+ tmpReg);
+ }
}
- return opType;
+ // Also, check for implicit operands used by the machine instruction
+ // (no need to check those defined since they cannot be constants).
+ // These include:
+ // -- arguments to a Call
+ // -- return value of a Return
+ // Any such operand that is a constant value needs to be fixed also.
+ // The current instructions with implicit refs (viz., Call and Return)
+ // have no immediate fields, so the constant always needs to be loaded
+ // into a register.
+ //
+ bool isCall = instrInfo.isCall(opCode);
+ unsigned lastCallArgNum = 0; // unused if not a call
+ CallArgsDescriptor* argDesc = NULL; // unused if not a call
+ if (isCall)
+ argDesc = CallArgsDescriptor::get(minstr);
+
+ for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
+ if (isa<Constant>(minstr->getImplicitRef(i)) ||
+ isa<GlobalValue>(minstr->getImplicitRef(i)))
+ {
+ Value* oldVal = minstr->getImplicitRef(i);
+ TmpInstruction* tmpReg =
+ InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
+ minstr->setImplicitRef(i, tmpReg);
+
+ if (isCall)
+ { // find and replace the argument in the CallArgsDescriptor
+ unsigned i=lastCallArgNum;
+ while (argDesc->getArgInfo(i).getArgVal() != oldVal)
+ ++i;
+ assert(i < argDesc->getNumArgs() &&
+ "Constant operands to a call *must* be in the arg list");
+ lastCallArgNum = i;
+ argDesc->getArgInfo(i).replaceArgVal(tmpReg);
+ }
+ }
+
+ return MVec;
}
-