-// $Id$ -*-c++-*-
-//***************************************************************************
-// File:
-// InstrSelectionSupport.h
+//===-- InstrSelectionSupport.cpp -----------------------------------------===//
+//
+// Target-independent instruction selection code. See SparcInstrSelection.cpp
+// for usage.
//
-// Purpose:
-// Target-independent instruction selection code.
-// See SparcInstrSelection.cpp for usage.
-//
-// History:
-// 10/10/01 - Vikram Adve - Created
-//**************************************************************************/
+//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/InstrSelection.h"
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrAnnot.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineRegInfo.h"
-#include "llvm/ConstPoolVals.h"
-#include "llvm/Instruction.h"
-#include "llvm/Type.h"
-#include "llvm/iMemory.h"
-
+#include "llvm/Target/TargetRegInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Constants.h"
+#include "llvm/BasicBlock.h"
+#include "llvm/DerivedTypes.h"
+using std::vector;
//*************************** Local Functions ******************************/
+// Generate code to load the constant into a TmpInstruction (virtual reg) and
+// returns the virtual register.
+//
static TmpInstruction*
-InsertCodeToLoadConstant(Value* opValue,
+InsertCodeToLoadConstant(Function *F,
+ Value* opValue,
Instruction* vmInstr,
vector<MachineInstr*>& loadConstVec,
TargetMachine& target)
{
- vector<TmpInstruction*> tempVec;
-
// Create a tmp virtual register to hold the constant.
- TmpInstruction* tmpReg =
- new TmpInstruction(TMP_INSTRUCTION_OPCODE, opValue, NULL);
- vmInstr->getMachineInstrVec().addTempValue(tmpReg);
+ TmpInstruction* tmpReg = new TmpInstruction(opValue);
+ MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
+ mcfi.addTemp(tmpReg);
- target.getInstrInfo().CreateCodeToLoadConst(opValue, tmpReg,
- loadConstVec, tempVec);
-
- // Register the new tmp values created for this m/c instruction sequence
- for (unsigned i=0; i < tempVec.size(); i++)
- vmInstr->getMachineInstrVec().addTempValue(tempVec[i]);
+ target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
+ loadConstVec, mcfi);
// Record the mapping from the tmp VM instruction to machine instruction.
// Do this for all machine instructions that were not mapped to any
}
-//---------------------------------------------------------------------------
-// Function GetConstantValueAsSignedInt
-//
-// Convenience function to get the value of an integer constant, for an
-// appropriate integer or non-integer type that can be held in an integer.
-// The type of the argument must be the following:
-// Signed or unsigned integer
-// Boolean
-// Pointer
-//
-// isValidConstant is set to true if a valid constant was found.
-//---------------------------------------------------------------------------
-
-int64_t
-GetConstantValueAsSignedInt(const Value *V,
- bool &isValidConstant)
+MachineOperand::MachineOperandType
+ChooseRegOrImmed(int64_t intValue,
+ bool isSigned,
+ MachineOpCode opCode,
+ const TargetMachine& target,
+ bool canUseImmed,
+ unsigned int& getMachineRegNum,
+ int64_t& getImmedValue)
{
- if (!isa<ConstPoolVal>(V))
- {
- isValidConstant = false;
- return 0;
- }
-
- isValidConstant = true;
-
- if (V->getType() == Type::BoolTy)
- return (int64_t) ((ConstPoolBool*)V)->getValue();
-
- if (V->getType()->isIntegral())
+ MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
+ getMachineRegNum = 0;
+ getImmedValue = 0;
+
+ if (canUseImmed &&
+ target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
{
- if (V->getType()->isSigned())
- return ((ConstPoolSInt*)V)->getValue();
-
- assert(V->getType()->isUnsigned());
- uint64_t Val = ((ConstPoolUInt*)V)->getValue();
- if (Val < INT64_MAX) // then safe to cast to signed
- return (int64_t)Val;
+ opType = isSigned? MachineOperand::MO_SignExtendedImmed
+ : MachineOperand::MO_UnextendedImmed;
+ getImmedValue = intValue;
}
-
- isValidConstant = false;
- return 0;
-}
-
-
-//---------------------------------------------------------------------------
-// Function: FoldGetElemChain
-//
-// Purpose:
-// Fold a chain of GetElementPtr instructions into an equivalent
-// (Pointer, IndexVector) pair. Returns the pointer Value, and
-// stores the resulting IndexVector in argument chainIdxVec.
-//---------------------------------------------------------------------------
-
-Value*
-FoldGetElemChain(const InstructionNode* getElemInstrNode,
- vector<ConstPoolVal*>& chainIdxVec)
-{
- MemAccessInst* getElemInst = (MemAccessInst*)
- getElemInstrNode->getInstruction();
-
- // Initialize return values from the incoming instruction
- Value* ptrVal = getElemInst->getPtrOperand();
- chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
-
- // Now chase the chain of getElementInstr instructions, if any
- InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
- while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
- ptrChild->getOpLabel() == GetElemPtrIdx)
+ else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
{
- // Child is a GetElemPtr instruction
- getElemInst = (MemAccessInst*)
- ((InstructionNode*) ptrChild)->getInstruction();
- const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
-
- // Get the pointer value out of ptrChild and *prepend* its index vector
- ptrVal = getElemInst->getPtrOperand();
- chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
-
- ptrChild = ptrChild->leftChild();
+ opType = MachineOperand::MO_MachineRegister;
+ getMachineRegNum = target.getRegInfo().getZeroRegNum();
}
-
- return ptrVal;
-}
-
-//------------------------------------------------------------------------
-// Function Set2OperandsFromInstr
-// Function Set3OperandsFromInstr
-//
-// For the common case of 2- and 3-operand arithmetic/logical instructions,
-// set the m/c instr. operands directly from the VM instruction's operands.
-// Check whether the first or second operand is 0 and can use a dedicated "0"
-// register.
-// Check whether the second operand should use an immediate field or register.
-// (First and third operands are never immediates for such instructions.)
-//
-// Arguments:
-// canDiscardResult: Specifies that the result operand can be discarded
-// by using the dedicated "0"
-//
-// op1position, op2position and resultPosition: Specify in which position
-// in the machine instruction the 3 operands (arg1, arg2
-// and result) should go.
-//
-// RETURN VALUE: unsigned int flags, where
-// flags & 0x01 => operand 1 is constant and needs a register
-// flags & 0x02 => operand 2 is constant and needs a register
-//------------------------------------------------------------------------
-
-void
-Set2OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& target,
- bool canDiscardResult,
- int op1Position,
- int resultPosition)
-{
- Set3OperandsFromInstr(minstr, vmInstrNode, target,
- canDiscardResult, op1Position,
- /*op2Position*/ -1, resultPosition);
-}
-
-
-void
-Set3OperandsFromInstr(MachineInstr* minstr,
- InstructionNode* vmInstrNode,
- const TargetMachine& target,
- bool canDiscardResult,
- int op1Position,
- int op2Position,
- int resultPosition)
-{
- assert(op1Position >= 0);
- assert(resultPosition >= 0);
-
- // operand 1
- minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
- vmInstrNode->leftChild()->getValue());
-
- // operand 2 (if any)
- if (op2Position >= 0)
- minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
- vmInstrNode->rightChild()->getValue());
-
- // result operand: if it can be discarded, use a dead register if one exists
- if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
- minstr->SetMachineOperand(resultPosition,
- target.getRegInfo().getZeroRegNum());
- else
- minstr->SetMachineOperand(resultPosition,
- MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
+ return opType;
}
unsigned int& getMachineRegNum,
int64_t& getImmedValue)
{
- MachineOperand::MachineOperandType opType =
- MachineOperand::MO_VirtualRegister;
getMachineRegNum = 0;
getImmedValue = 0;
-
- // Check for the common case first: argument is not constant
- //
- ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
- if (!CPV) return opType;
-
- if (CPV->getType() == Type::BoolTy)
- {
- ConstPoolBool *CPB = (ConstPoolBool*)CPV;
- if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
- {
- getMachineRegNum = target.getRegInfo().getZeroRegNum();
- return MachineOperand::MO_MachineRegister;
- }
- getImmedValue = 1;
- return MachineOperand::MO_SignExtendedImmed;
- }
-
- if (!CPV->getType()->isIntegral()) return opType;
+ // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
+ Constant *CPV = dyn_cast<Constant>(val);
+ if (CPV == NULL ||
+ (! CPV->getType()->isIntegral() &&
+ ! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
+ return MachineOperand::MO_VirtualRegister;
// Now get the constant value and check if it fits in the IMMED field.
// Take advantage of the fact that the max unsigned value will rarely
// unsigned constants to signed).
//
int64_t intValue;
- if (CPV->getType()->isSigned())
- {
- intValue = ((ConstPoolSInt*)CPV)->getValue();
- }
+ if (isa<PointerType>(CPV->getType()))
+ intValue = 0; // We checked above that it is NULL
+ else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
+ intValue = (int64_t) CB->getValue();
+ else if (CPV->getType()->isSigned())
+ intValue = cast<ConstantSInt>(CPV)->getValue();
else
- {
- uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
- if (V >= INT64_MAX) return opType;
- intValue = (int64_t)V;
+ { // get the int value and sign-extend if original was less than 64 bits
+ intValue = (int64_t) cast<ConstantUInt>(CPV)->getValue();
+ switch(CPV->getType()->getPrimitiveID())
+ {
+ case Type::UByteTyID: intValue = (int64_t) (int8_t) intValue; break;
+ case Type::UShortTyID: intValue = (int64_t) (short) intValue; break;
+ case Type::UIntTyID: intValue = (int64_t) (int) intValue; break;
+ default: break;
+ }
}
- if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
- {
- opType = MachineOperand::MO_MachineRegister;
- getMachineRegNum = target.getRegInfo().getZeroRegNum();
- }
- else if (canUseImmed &&
- target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
- {
- opType = MachineOperand::MO_SignExtendedImmed;
- getImmedValue = intValue;
- }
-
- return opType;
+ return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
+ opCode, target, canUseImmed,
+ getMachineRegNum, getImmedValue);
}
+
//---------------------------------------------------------------------------
// Function: FixConstantOperandsForInstr
//
MachineInstr* minstr,
TargetMachine& target)
{
- vector<MachineInstr*> loadConstVec;
-
- const MachineInstrDescriptor& instrDesc =
- target.getInstrInfo().getDescriptor(minstr->getOpCode());
+ vector<MachineInstr*> MVec;
+ MachineOpCode opCode = minstr->getOpCode();
+ const TargetInstrInfo& instrInfo = target.getInstrInfo();
+ int resultPos = instrInfo.getResultPos(opCode);
+ int immedPos = instrInfo.getImmedConstantPos(opCode);
+
+ Function *F = vmInstr->getParent()->getParent();
+
for (unsigned op=0; op < minstr->getNumOperands(); op++)
{
const MachineOperand& mop = minstr->getOperand(op);
- // skip the result position (for efficiency below) and any other
- // positions already marked as not a virtual register
- if (instrDesc.resultPos == (int) op ||
- mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
- mop.getVRegValue() == NULL)
+ // Skip the result position, preallocated machine registers, or operands
+ // that cannot be constants (CC regs or PC-relative displacements)
+ if (resultPos == (int)op ||
+ mop.getType() == MachineOperand::MO_MachineRegister ||
+ mop.getType() == MachineOperand::MO_CCRegister ||
+ mop.getType() == MachineOperand::MO_PCRelativeDisp)
+ continue;
+
+ bool constantThatMustBeLoaded = false;
+ unsigned int machineRegNum = 0;
+ int64_t immedValue = 0;
+ Value* opValue = NULL;
+ MachineOperand::MachineOperandType opType =
+ MachineOperand::MO_VirtualRegister;
+
+ // Operand may be a virtual register or a compile-time constant
+ if (mop.getType() == MachineOperand::MO_VirtualRegister)
{
- continue;
+ assert(mop.getVRegValue() != NULL);
+ opValue = mop.getVRegValue();
+ if (Constant *opConst = dyn_cast<Constant>(opValue)) {
+ opType = ChooseRegOrImmed(opConst, opCode, target,
+ (immedPos == (int)op), machineRegNum,
+ immedValue);
+ if (opType == MachineOperand::MO_VirtualRegister)
+ constantThatMustBeLoaded = true;
+ }
}
-
- Value* opValue = mop.getVRegValue();
- bool constantThatMustBeLoaded = false;
-
- if (isa<ConstPoolVal>(opValue))
+ else
{
- unsigned int machineRegNum;
- int64_t immedValue;
- MachineOperand::MachineOperandType opType =
- ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
- /*canUseImmed*/ (op == 1),
- machineRegNum, immedValue);
-
- if (opType == MachineOperand::MO_MachineRegister)
- minstr->SetMachineOperand(op, machineRegNum);
- else if (opType == MachineOperand::MO_VirtualRegister)
- constantThatMustBeLoaded = true; // load is generated below
- else
- minstr->SetMachineOperand(op, opType, immedValue);
+ assert(mop.isImmediate());
+ bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
+
+ // Bit-selection flags indicate an instruction that is extracting
+ // bits from its operand so ignore this even if it is a big constant.
+ if (mop.opHiBits32() || mop.opLoBits32() ||
+ mop.opHiBits64() || mop.opLoBits64())
+ continue;
+
+ opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
+ opCode, target, (immedPos == (int)op),
+ machineRegNum, immedValue);
+
+ if (opType == mop.getType())
+ continue; // no change: this is the most common case
+
+ if (opType == MachineOperand::MO_VirtualRegister)
+ {
+ constantThatMustBeLoaded = true;
+ opValue = isSigned
+ ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
+ : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
+ }
}
- if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
- { // opValue is a constant that must be explicitly loaded into a reg.
- TmpInstruction* tmpReg = InsertCodeToLoadConstant(opValue, vmInstr,
- loadConstVec, target);
- minstr->SetMachineOperand(op, MachineOperand::MO_VirtualRegister,
- tmpReg);
+ if (opType == MachineOperand::MO_MachineRegister)
+ minstr->SetMachineOperandReg(op, machineRegNum);
+ else if (opType == MachineOperand::MO_SignExtendedImmed ||
+ opType == MachineOperand::MO_UnextendedImmed)
+ minstr->SetMachineOperandConst(op, opType, immedValue);
+ else if (constantThatMustBeLoaded ||
+ (opValue && isa<GlobalValue>(opValue)))
+ { // opValue is a constant that must be explicitly loaded into a reg
+ assert(opValue);
+ TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
+ MVec, target);
+ minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
+ tmpReg);
}
}
- //
- // Also, check for implicit operands used (not those defined) by the
- // machine instruction. These include:
+ // Also, check for implicit operands used by the machine instruction
+ // (no need to check those defined since they cannot be constants).
+ // These include:
// -- arguments to a Call
// -- return value of a Return
// Any such operand that is a constant value needs to be fixed also.
// have no immediate fields, so the constant always needs to be loaded
// into a register.
//
+ bool isCall = instrInfo.isCall(opCode);
+ unsigned lastCallArgNum = 0; // unused if not a call
+ CallArgsDescriptor* argDesc = NULL; // unused if not a call
+ if (isCall)
+ argDesc = CallArgsDescriptor::get(minstr);
+
for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
- if (isa<ConstPoolVal>(minstr->getImplicitRef(i)) ||
+ if (isa<Constant>(minstr->getImplicitRef(i)) ||
isa<GlobalValue>(minstr->getImplicitRef(i)))
{
+ Value* oldVal = minstr->getImplicitRef(i);
TmpInstruction* tmpReg =
- InsertCodeToLoadConstant(minstr->getImplicitRef(i), vmInstr,
- loadConstVec, target);
+ InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
minstr->setImplicitRef(i, tmpReg);
+
+ if (isCall)
+ { // find and replace the argument in the CallArgsDescriptor
+ unsigned i=lastCallArgNum;
+ while (argDesc->getArgInfo(i).getArgVal() != oldVal)
+ ++i;
+ assert(i < argDesc->getNumArgs() &&
+ "Constant operands to a call *must* be in the arg list");
+ lastCallArgNum = i;
+ argDesc->getArgInfo(i).replaceArgVal(tmpReg);
+ }
}
- return loadConstVec;
-}
-
-
-#undef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
-#ifdef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
-unsigned
-FixConstantOperands(const InstructionNode* vmInstrNode,
- TargetMachine& target)
-{
- Instruction* vmInstr = vmInstrNode->getInstruction();
- MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec();
-
- for (unsigned i=0; i < mvec.size(); i++)
- {
- vector<MachineInsr*> loadConstVec =
- FixConstantOperandsForInstr(mvec[i], target);
- }
-
- //
- // Finally, inserted the generated instructions in the vector
- // to be returned.
- //
- unsigned numNew = loadConstVec.size();
- if (numNew > 0)
- {
- // Insert the new instructions *before* the old ones by moving
- // the old ones over `numNew' positions (last-to-first, of course!).
- // We do check *after* returning that we did not exceed the vector mvec.
- for (int i=numInstr-1; i >= 0; i--)
- mvec[i+numNew] = mvec[i];
-
- for (unsigned i=0; i < numNew; i++)
- mvec[i] = loadConstVec[i];
- }
-
- return (numInstr + numNew);
+ return MVec;
}
-#endif SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
-
-
projects / oota-llvm.git / blobdiff