#include "llvm/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Assembly/PrintModulePass.h"
-#include "llvm/Analysis/LoopPass.h"
+#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
bool EnableFastISel;
}
+static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
+ cl::desc("Disable Post Regalloc"));
+static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
+ cl::desc("Disable branch folding"));
+static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
+ cl::desc("Disable tail duplication"));
+static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
+ cl::desc("Disable code placement"));
+static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
+ cl::desc("Disable Stack Slot Coloring"));
+static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
+ cl::desc("Disable Machine LICM"));
+static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
+ cl::desc("Disable Machine Sinking"));
+static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
+ cl::desc("Disable Loop Strength Reduction Pass"));
+static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
+ cl::desc("Disable Codegen Prepare"));
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// When this works it will be on by default.
-static cl::opt<bool>
-DisablePostRAScheduler("disable-post-RA-scheduler",
- cl::desc("Disable scheduling after register allocation"),
- cl::init(true));
-
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
-// able to enable or disable fast-isel independently from -fast.
+// able to enable or disable fast-isel independently from -O0.
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
- cl::desc("Enable the experimental \"fast\" instruction selector"));
+ cl::desc("Enable the \"fast\" instruction selector"));
+
+// Enable or disable an experimental optimization to split GEPs
+// and run a special GVN pass which does not examine loads, in
+// an effort to factor out redundancy implicit in complex GEPs.
+static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
+ cl::desc("Split GEPs and run no-load GVN"));
+
+static cl::opt<bool> PreAllocTailDup("pre-regalloc-taildup", cl::Hidden,
+ cl::desc("Pre-register allocation tail duplication"));
+
+LLVMTargetMachine::LLVMTargetMachine(const Target &T,
+ const std::string &TargetTriple)
+ : TargetMachine(T) {
+ AsmInfo = T.createAsmInfo(TargetTriple);
+}
+
+
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
- // Fold redundant debug labels.
- PM.add(createDebugLabelFoldingPass());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (OptLevel != CodeGenOpt::None)
- PM.add(createCodePlacementOptPass());
-
switch (FileType) {
default:
break;
CodeGenOpt::Level OptLevel,
bool Verbose,
formatted_raw_ostream &Out) {
- FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
+ FunctionPass *Printer =
+ getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
if (!Printer)
return true;
if (addCommonCodeGenPasses(PM, OptLevel))
return true;
- if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
addCodeEmitter(PM, OptLevel, MCE);
if (PrintEmittedAsm)
addAssemblyEmitter(PM, OptLevel, true, ferrs());
if (addCommonCodeGenPasses(PM, OptLevel))
return true;
- if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
addCodeEmitter(PM, OptLevel, JCE);
if (PrintEmittedAsm)
addAssemblyEmitter(PM, OptLevel, true, ferrs());
}
static void printAndVerify(PassManagerBase &PM,
+ const char *Banner,
bool allowDoubleDefs = false) {
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ PM.add(createMachineFunctionPrinterPass(errs(), Banner));
if (VerifyMachineCode)
PM.add(createMachineVerifierPass(allowDoubleDefs));
CodeGenOpt::Level OptLevel) {
// Standard LLVM-Level Passes.
+ // Optionally, tun split-GEPs and no-load GVN.
+ if (EnableSplitGEPGVN) {
+ PM.add(createGEPSplitterPass());
+ PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
+ }
+
// Run loop strength reduction before anything else.
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
// Turn exception handling constructs into something the code generators can
// handle.
- if (!getTargetAsmInfo()->doesSupportExceptionHandling())
- PM.add(createLowerInvokePass(getTargetLowering()));
- else
+ switch (getMCAsmInfo()->getExceptionHandlingType())
+ {
+ case ExceptionHandling::SjLj:
+ // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+ PM.add(createSjLjEHPass(getTargetLowering()));
+ break;
+ case ExceptionHandling::Dwarf:
+ PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+ break;
+ case ExceptionHandling::None:
+ PM.add(createLowerInvokePass(getTargetLowering()));
+ break;
+ }
PM.add(createGCLoweringPass());
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- if (OptLevel != CodeGenOpt::None)
+ if (OptLevel != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
return true;
// Print the instruction selected machine code...
- printAndVerify(PM, /* allowDoubleDefs= */ true);
+ printAndVerify(PM, "After Instruction Selection",
+ /* allowDoubleDefs= */ true);
if (OptLevel != CodeGenOpt::None) {
- PM.add(createMachineLICMPass());
- PM.add(createMachineSinkingPass());
- printAndVerify(PM, /* allowDoubleDefs= */ true);
+ if (!DisableMachineLICM)
+ PM.add(createMachineLICMPass());
+ if (!DisableMachineSink)
+ PM.add(createMachineSinkingPass());
+ printAndVerify(PM, "After MachineLICM and MachineSinking",
+ /* allowDoubleDefs= */ true);
+ }
+
+ // Pre-ra tail duplication.
+ if (OptLevel != CodeGenOpt::None &&
+ !DisableTailDuplicate && PreAllocTailDup) {
+ PM.add(createTailDuplicatePass(true));
+ printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
}
// Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel))
- printAndVerify(PM);
+ printAndVerify(PM, "After PreRegAlloc passes",
+ /* allowDoubleDefs= */ true);
// Perform register allocation.
PM.add(createRegisterAllocator());
+ printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring.
- if (OptLevel != CodeGenOpt::None)
- PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
-
- printAndVerify(PM); // Print the register-allocated code
+ if (OptLevel != CodeGenOpt::None && !DisableSSC) {
+ // FIXME: Re-enable coloring with register when it's capable of adding
+ // kill markers.
+ PM.add(createStackSlotColoringPass(false));
+ printAndVerify(PM, "After StackSlotColoring");
+ }
// Run post-ra passes.
if (addPostRegAlloc(PM, OptLevel))
- printAndVerify(PM);
+ printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createLowerSubregsPass());
- printAndVerify(PM);
+ printAndVerify(PM, "After LowerSubregs");
// Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter());
- printAndVerify(PM);
+ printAndVerify(PM, "After PrologEpilogCodeInserter");
+
+ // Run pre-sched2 passes.
+ if (addPreSched2(PM, OptLevel))
+ printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
- PM.add(createPostRAScheduler());
- printAndVerify(PM);
+ if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
+ PM.add(createPostRAScheduler(OptLevel));
+ printAndVerify(PM, "After PostRAScheduler");
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
- printAndVerify(PM);
+ printAndVerify(PM, "After BranchFolding");
+ }
+
+ // Tail duplication.
+ if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
+ PM.add(createTailDuplicatePass(false));
+ printAndVerify(PM, "After TailDuplicate");
}
PM.add(createGCMachineCodeAnalysisPass());
- printAndVerify(PM);
if (PrintGCInfo)
- PM.add(createGCInfoPrinter(*cerr));
+ PM.add(createGCInfoPrinter(errs()));
+
+ if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
+ PM.add(createCodePlacementOptPass());
+ printAndVerify(PM, "After CodePlacementOpt");
+ }
+
+ if (addPreEmitPass(PM, OptLevel))
+ printAndVerify(PM, "After PreEmit passes");
return false;
}