Testcase for PR2264.

[oota-llvm.git] / lib / CodeGen / LLVMTargetMachine.cpp

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 32fbc15e1315aee039b6b4e02a78e8ee9f8f7632..4004cf1e1800a3e5b0f8eca818262089f6a64bf2 100644 (file)
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/Collector.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
@@ -51,7 +52,7 @@ DisablePostRAScheduler("disable-post-RA-scheduler",
                        cl::init(true));
 
 FileModel::Model
-LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
+LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        std::ostream &Out,
                                        CodeGenFileType FileType,
                                        bool Fast) {
@@ -61,12 +62,12 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
   }
   
   PM.add(createGCLoweringPass());
 
-  if (!ExceptionHandling)
+  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
     PM.add(createLowerInvokePass(getTargetLowering()));
 
   // Make sure that no unreachable blocks are instruction selected.
@@ -76,7 +77,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
+    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
                                  &cerr));
   
   // Ask the target for an isel.
@@ -93,6 +94,10 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   if (EnableSinking)
     PM.add(createMachineSinkingPass());
 
+  // Run pre-ra passes.
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
@@ -135,7 +140,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (AlignLoops)
+  if (AlignLoops && !OptimizeForSize)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -158,7 +163,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 /// be split up (e.g., to add an object writer pass), this method can be used to
 /// finish up adding passes to emit the file, if necessary.
-bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
+bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
                                                   MachineCodeEmitter *MCE,
                                                   bool Fast) {
   if (MCE)
@@ -178,7 +183,7 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
 /// of functions.  This method should returns true if machine code emission is
 /// not supported.
 ///
-bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
                                                    MachineCodeEmitter &MCE,
                                                    bool Fast) {
   // Standard LLVM-Level Passes.
@@ -187,12 +192,12 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
   }
   
   PM.add(createGCLoweringPass());
   
-  if (!ExceptionHandling)
+  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
     PM.add(createLowerInvokePass(getTargetLowering()));
   
   // Make sure that no unreachable blocks are instruction selected.
@@ -202,7 +207,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
+    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
                                  &cerr));
 
   // Ask the target for an isel.
@@ -219,6 +224,10 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   if (EnableSinking)
     PM.add(createMachineSinkingPass());
 
+  // Run pre-ra passes.
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());