#include "llvm/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Assembly/PrintModulePass.h"
-#include "llvm/Analysis/LoopPass.h"
+#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/FileWriters.h"
#include "llvm/CodeGen/GCStrategy.h"
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/Target/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/FormattedStream.h"
using namespace llvm;
namespace llvm {
bool EnableFastISel;
}
+static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
+ cl::desc("Disable Post Regalloc"));
+static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
+ cl::desc("Disable branch folding"));
+static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
+ cl::desc("Disable tail duplication"));
+static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
+ cl::desc("Disable pre-register allocation tail duplication"));
+static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
+ cl::desc("Disable code placement"));
+static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
+ cl::desc("Disable Stack Slot Coloring"));
+static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
+ cl::desc("Disable Machine LICM"));
+static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
+ cl::desc("Disable Machine Sinking"));
+static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
+ cl::desc("Disable Loop Strength Reduction Pass"));
+static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
+ cl::desc("Disable Codegen Prepare"));
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
-static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
- cl::desc("Dump emitter generated instructions as assembly"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
+static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
+ cl::desc("Verify generated machine code"),
+ cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// When this works it will be on by default.
-static cl::opt<bool>
-DisablePostRAScheduler("disable-post-RA-scheduler",
- cl::desc("Disable scheduling after register allocation"),
- cl::init(true));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
-// able to enable or disable fast-isel independently from -fast.
+// able to enable or disable fast-isel independently from -O0.
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
- cl::desc("Enable the experimental \"fast\" instruction selector"));
+ cl::desc("Enable the \"fast\" instruction selector"));
+
+// Enable or disable an experimental optimization to split GEPs
+// and run a special GVN pass which does not examine loads, in
+// an effort to factor out redundancy implicit in complex GEPs.
+static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
+ cl::desc("Split GEPs and run no-load GVN"));
+
+LLVMTargetMachine::LLVMTargetMachine(const Target &T,
+ const std::string &TargetTriple)
+ : TargetMachine(T) {
+ AsmInfo = T.createAsmInfo(TargetTriple);
+}
+
+// Set the default code model for the JIT for a generic target.
+// FIXME: Is small right here? or .is64Bit() ? Large : Small?
+void
+LLVMTargetMachine::setCodeModelForJIT() {
+ setCodeModel(CodeModel::Small);
+}
+
+// Set the default code model for static compilation for a generic target.
+void
+LLVMTargetMachine::setCodeModelForStatic() {
+ setCodeModel(CodeModel::Small);
+}
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
- raw_ostream &Out,
+ formatted_raw_ostream &Out,
CodeGenFileType FileType,
- bool Fast) {
+ CodeGenOpt::Level OptLevel) {
// Add common CodeGen passes.
- if (addCommonCodeGenPasses(PM, Fast))
+ if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
- // Fold redundant debug labels.
- PM.add(createDebugLabelFoldingPass());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (addPreEmitPass(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (!Fast)
- PM.add(createLoopAlignerPass());
-
+ FileModel::Model ResultTy;
switch (FileType) {
default:
- break;
- case TargetMachine::AssemblyFile:
- if (addAssemblyEmitter(PM, Fast, Out))
- return FileModel::Error;
- return FileModel::AsmFile;
+ return FileModel::Error;
case TargetMachine::ObjectFile:
- if (getMachOWriterInfo())
- return FileModel::MachOFile;
- else if (getELFWriterInfo())
- return FileModel::ElfFile;
+ return FileModel::Error;
+ case TargetMachine::AssemblyFile: {
+ FunctionPass *Printer =
+ getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(),
+ getAsmVerbosityDefault());
+ if (Printer == 0) return FileModel::Error;
+ PM.add(Printer);
+ ResultTy = FileModel::AsmFile;
+ break;
}
-
- return FileModel::Error;
-}
-
-/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
-/// be split up (e.g., to add an object writer pass), this method can be used to
-/// finish up adding passes to emit the file, if necessary.
-bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
- MachineCodeEmitter *MCE,
- bool Fast) {
- if (MCE)
- addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
-
+ }
+
+ // Make sure the code model is set.
+ setCodeModelForStatic();
PM.add(createGCInfoDeleter());
-
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
-
- return false; // success!
+ return ResultTy;
}
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
/// not supported.
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
- MachineCodeEmitter &MCE,
- bool Fast) {
+ JITCodeEmitter &JCE,
+ CodeGenOpt::Level OptLevel) {
+ // Make sure the code model is set.
+ setCodeModelForJIT();
+
// Add common CodeGen passes.
- if (addCommonCodeGenPasses(PM, Fast))
+ if (addCommonCodeGenPasses(PM, OptLevel))
return true;
- if (addPreEmitPass(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
-
+ addCodeEmitter(PM, OptLevel, JCE);
PM.add(createGCInfoDeleter());
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
-
return false; // success!
}
-/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
-/// both emitting to assembly files or machine code output.
+static void printAndVerify(PassManagerBase &PM,
+ const char *Banner,
+ bool allowDoubleDefs = false) {
+ if (PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
+
+ if (VerifyMachineCode)
+ PM.add(createMachineVerifierPass(allowDoubleDefs));
+}
+
+/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
+/// emitting to assembly files or machine code output.
///
-bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
+bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Standard LLVM-Level Passes.
+ // Optionally, tun split-GEPs and no-load GVN.
+ if (EnableSplitGEPGVN) {
+ PM.add(createGEPSplitterPass());
+ PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
+ }
+
// Run loop strength reduction before anything else.
- if (!Fast) {
+ if (OptLevel != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
- PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
+ PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
- PM.add(createGCLoweringPass());
-
- if (!getTargetAsmInfo()->doesSupportExceptionHandling())
+ // Turn exception handling constructs into something the code generators can
+ // handle.
+ switch (getMCAsmInfo()->getExceptionHandlingType())
+ {
+ case ExceptionHandling::SjLj:
+ // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
+ // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
+ // catch info can get misplaced when a selector ends up more than one block
+ // removed from the parent invoke(s). This could happen when a landing
+ // pad is shared by multiple invokes and is also a target of a normal
+ // edge from elsewhere.
+ PM.add(createSjLjEHPass(getTargetLowering()));
+ PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+ break;
+ case ExceptionHandling::Dwarf:
+ PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+ break;
+ case ExceptionHandling::None:
PM.add(createLowerInvokePass(getTargetLowering()));
+ break;
+ }
+
+ PM.add(createGCLoweringPass());
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- if (!Fast)
+ if (OptLevel != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
- &errs()));
+ &dbgs()));
// Standard Lower-Level Passes.
+ // Set up a MachineFunction for the rest of CodeGen to work on.
+ PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
- (Fast && EnableFastISelOption != cl::BOU_FALSE))
+ (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
// Ask the target for an isel.
- if (addInstSelector(PM, Fast))
+ if (addInstSelector(PM, OptLevel))
return true;
// Print the instruction selected machine code...
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ printAndVerify(PM, "After Instruction Selection",
+ /* allowDoubleDefs= */ true);
+
+ if (OptLevel != CodeGenOpt::None) {
+ PM.add(createOptimizeExtsPass());
+ if (!DisableMachineLICM)
+ PM.add(createMachineLICMPass());
+ if (!DisableMachineSink)
+ PM.add(createMachineSinkingPass());
+ printAndVerify(PM, "After MachineLICM and MachineSinking",
+ /* allowDoubleDefs= */ true);
+ }
- if (!Fast) {
- PM.add(createMachineLICMPass());
- PM.add(createMachineSinkingPass());
+ // Pre-ra tail duplication.
+ if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
+ PM.add(createTailDuplicatePass(true));
+ printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
+ /* allowDoubleDefs= */ true);
}
// Run pre-ra passes.
- if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (addPreRegAlloc(PM, OptLevel))
+ printAndVerify(PM, "After PreRegAlloc passes",
+ /* allowDoubleDefs= */ true);
// Perform register allocation.
PM.add(createRegisterAllocator());
+ printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring.
- if (!Fast)
- PM.add(createStackSlotColoringPass());
-
- if (PrintMachineCode) // Print the register-allocated code
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (OptLevel != CodeGenOpt::None && !DisableSSC) {
+ // FIXME: Re-enable coloring with register when it's capable of adding
+ // kill markers.
+ PM.add(createStackSlotColoringPass(false));
+ printAndVerify(PM, "After StackSlotColoring");
+ }
// Run post-ra passes.
- if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (addPostRegAlloc(PM, OptLevel))
+ printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createLowerSubregsPass());
-
- if (PrintMachineCode) // Print the subreg lowered code
- PM.add(createMachineFunctionPrinterPass(cerr));
+ printAndVerify(PM, "After LowerSubregs");
// Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter());
+ printAndVerify(PM, "After PrologEpilogCodeInserter");
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ // Run pre-sched2 passes.
+ if (addPreSched2(PM, OptLevel))
+ printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler.
- if (!Fast && !DisablePostRAScheduler) {
- PM.add(createPostRAScheduler());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
+ PM.add(createPostRAScheduler(OptLevel));
+ printAndVerify(PM, "After PostRAScheduler");
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (!Fast)
+ if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
+ printAndVerify(PM, "After BranchFolding");
+ }
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
+ // Tail duplication.
+ if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
+ PM.add(createTailDuplicatePass(false));
+ printAndVerify(PM, "After TailDuplicate");
+ }
PM.add(createGCMachineCodeAnalysisPass());
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(cerr));
-
if (PrintGCInfo)
- PM.add(createGCInfoPrinter(*cerr));
+ PM.add(createGCInfoPrinter(dbgs()));
+
+ if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
+ PM.add(createCodePlacementOptPass());
+ printAndVerify(PM, "After CodePlacementOpt");
+ }
+
+ if (addPreEmitPass(PM, OptLevel))
+ printAndVerify(PM, "After PreEmit passes");
return false;
}
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