cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
+static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
+ cl::desc("Dump emitter generated instructions as assembly"));
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(createLowerSubregsPass());
+
+ if (PrintMachineCode) // Print the subreg lowered code
+ PM.add(createMachineFunctionPrinterPass(cerr));
// Run post-ra passes.
if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
PM.add(createPrologEpilogCodeInserter());
// Second pass scheduler.
- PM.add(createPostRAScheduler());
+ if (!Fast)
+ PM.add(createPostRAScheduler());
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (!Fast)
MachineCodeEmitter *MCE,
bool Fast) {
if (MCE)
- addSimpleCodeEmitter(PM, Fast, *MCE);
+ addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
// Delete machine code for this function
PM.add(createMachineCodeDeleter());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
+
+ PM.add(createLowerSubregsPass());
+
+ if (PrintMachineCode) // Print the subreg lowered code
+ PM.add(createMachineFunctionPrinterPass(cerr));
// Run post-ra passes.
if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
// Second pass scheduler.
- PM.add(createPostRAScheduler());
+ if (!Fast)
+ PM.add(createPostRAScheduler());
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (!Fast)
if (addPreEmitPass(PM, Fast) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- addCodeEmitter(PM, Fast, MCE);
+ addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
// Delete machine code for this function
PM.add(createMachineCodeDeleter());