Get rid of one more non-DebugLoc getNode and

[oota-llvm.git] / lib / CodeGen / LLVMTargetMachine.cpp

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 60925f31ddf0347a4b568ba328d95fefd5ddd92f..7def8fa61d2a3c57f825a4c7a656519e41b07b7c 100644 (file)
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -25,6 +25,10 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+namespace llvm {
+  bool EnableFastISel;
+}
+
 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
@@ -38,10 +42,6 @@ static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
 static cl::opt<bool>
 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
               cl::desc("Perform sinking on machine code"));
-static cl::opt<bool>
-EnableLICM("machine-licm",
-           cl::init(false), cl::Hidden,
-           cl::desc("Perform loop-invariant code motion on machine code"));
 
 // When this works it will be on by default.
 static cl::opt<bool>
@@ -49,6 +49,13 @@ DisablePostRAScheduler("disable-post-RA-scheduler",
                        cl::desc("Disable scheduling after register allocation"),
                        cl::init(true));
 
+// Enable or disable FastISel. Both options are needed, because
+// FastISel is enabled by default with -fast, and we wish to be
+// able to enable or disable fast-isel independently from -fast.
+static cl::opt<cl::boolOrDefault>
+EnableFastISelOption("fast-isel", cl::Hidden,
+  cl::desc("Enable the experimental \"fast\" instruction selector"));
+
 FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
                                        raw_ostream &Out,
@@ -67,7 +74,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast && !OptimizeForSize)
+  if (!Fast)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -140,7 +147,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
+      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
   }
 
   PM.add(createGCLoweringPass());
@@ -154,12 +161,20 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (!Fast)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
+  PM.add(createStackProtectorPass(getTargetLowering()));
+
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
-                                 &cerr));
+    PM.add(createPrintFunctionPass("\n\n"
+                                   "*** Final LLVM Code input to ISel ***\n",
+                                   &errs()));
 
   // Standard Lower-Level Passes.
 
+  // Enable FastISel with -fast, but allow that to be overridden.
+  if (EnableFastISelOption == cl::BOU_TRUE ||
+      (Fast && EnableFastISelOption != cl::BOU_FALSE))
+    EnableFastISel = true;
+
   // Ask the target for an isel.
   if (addInstSelector(PM, Fast))
     return true;
@@ -168,7 +183,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (EnableLICM)
+  if (!Fast)
     PM.add(createMachineLICMPass());
 
   if (EnableSinking)
@@ -207,13 +222,20 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (!Fast && !DisablePostRAScheduler)
+  if (!Fast && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
+    if (PrintMachineCode)
+      PM.add(createMachineFunctionPrinterPass(cerr));
+  }
+
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   PM.add(createGCMachineCodeAnalysisPass());
 
   if (PrintMachineCode)