Get rid of 3 non-DebugLoc getNode variants.

[oota-llvm.git] / lib / CodeGen / LLVMTargetMachine.cpp

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index bd8d499973510b3cb506a8f998ce8ed69d7035a3..c9ff15d4947f021aac7cc205d237fa293af11bc4 100644 (file)
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -56,12 +56,9 @@ DisablePostRAScheduler("disable-post-RA-scheduler",
 // Enable or disable FastISel. Both options are needed, because
 // FastISel is enabled by default with -fast, and we wish to be
 // able to enable or disable fast-isel independently from -fast.
-static cl::opt<bool>
+static cl::opt<cl::boolOrDefault>
 EnableFastISelOption("fast-isel", cl::Hidden,
   cl::desc("Enable the experimental \"fast\" instruction selector"));
-static cl::opt<bool>
-DisableFastISelOption("disable-fast-isel", cl::Hidden,
-  cl::desc("Disable the experimental \"fast\" instruction selector"));
 
 FileModel::Model
 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
@@ -81,7 +78,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (!Fast && !OptimizeForSize)
+  if (!Fast)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -154,7 +151,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
+      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
   }
 
   PM.add(createGCLoweringPass());
@@ -168,17 +165,18 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (!Fast)
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
+  PM.add(createStackProtectorPass(getTargetLowering()));
+
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
-                                 &cerr));
+    PM.add(createPrintFunctionPass("\n\n"
+                                   "*** Final LLVM Code input to ISel ***\n",
+                                   &errs()));
 
   // Standard Lower-Level Passes.
 
   // Enable FastISel with -fast, but allow that to be overridden.
-  assert((!EnableFastISelOption || !DisableFastISelOption) &&
-         "Both -fast-isel and -disable-fast-isel given!");
-  if (EnableFastISelOption ||
-      (Fast && !DisableFastISelOption))
+  if (EnableFastISelOption == cl::BOU_TRUE ||
+      (Fast && EnableFastISelOption != cl::BOU_FALSE))
     EnableFastISel = true;
 
   // Ask the target for an isel.
@@ -189,10 +187,6 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  // If we're using Fast-ISel, clean up the mess.
-  if (EnableFastISel)
-    PM.add(createDeadMachineInstructionElimPass());
-
   if (EnableLICM)
     PM.add(createMachineLICMPass());
 
@@ -232,13 +226,20 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
     PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Second pass scheduler.
-  if (!Fast && !DisablePostRAScheduler)
+  if (!Fast && !DisablePostRAScheduler) {
     PM.add(createPostRAScheduler());
 
+    if (PrintMachineCode)
+      PM.add(createMachineFunctionPrinterPass(cerr));
+  }
+
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   PM.add(createGCMachineCodeAnalysisPass());
 
   if (PrintMachineCode)