//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "VirtRegMap.h"
#include "llvm/Value.h"
-#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
#include <cmath>
-#include <iostream>
using namespace llvm;
-namespace {
- RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
-
- static Statistic<> numIntervals
- ("liveintervals", "Number of original intervals");
-
- static Statistic<> numIntervalsAfter
- ("liveintervals", "Number of intervals after coalescing");
+// Hidden options for help debugging.
+static cl::opt<bool> DisableReMat("disable-rematerialization",
+ cl::init(false), cl::Hidden);
- static Statistic<> numJoins
- ("liveintervals", "Number of interval joins performed");
+static cl::opt<bool> SplitAtBB("split-intervals-at-bb",
+ cl::init(true), cl::Hidden);
+static cl::opt<int> SplitLimit("split-limit",
+ cl::init(-1), cl::Hidden);
- static Statistic<> numPeep
- ("liveintervals", "Number of identity moves eliminated after coalescing");
+STATISTIC(numIntervals, "Number of original intervals");
+STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
+STATISTIC(numFolds , "Number of loads/stores folded into instructions");
+STATISTIC(numSplits , "Number of intervals split");
- static Statistic<> numFolded
- ("liveintervals", "Number of loads/stores folded into instructions");
-
- static cl::opt<bool>
- EnableJoining("join-liveintervals",
- cl::desc("Join compatible live intervals"),
- cl::init(true));
-}
+char LiveIntervals::ID = 0;
+static RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
-void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
-{
+void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
AU.addPreservedID(PHIEliminationID);
AU.addRequiredID(PHIEliminationID);
AU.addRequiredID(TwoAddressInstructionPassID);
- AU.addRequired<LoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
-void LiveIntervals::releaseMemory()
-{
+void LiveIntervals::releaseMemory() {
+ MBB2IdxMap.clear();
+ Idx2MBBMap.clear();
mi2iMap_.clear();
i2miMap_.clear();
r2iMap_.clear();
- r2rMap_.clear();
+ // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
+ VNInfoAllocator.Reset();
+ for (unsigned i = 0, e = ClonedMIs.size(); i != e; ++i)
+ delete ClonedMIs[i];
}
-
-static bool isZeroLengthInterval(LiveInterval *li) {
- for (LiveInterval::Ranges::const_iterator
- i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
- if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
- return false;
- return true;
+void LiveIntervals::computeNumbering() {
+ Index2MiMap OldI2MI = i2miMap_;
+
+ Idx2MBBMap.clear();
+ MBB2IdxMap.clear();
+ mi2iMap_.clear();
+ i2miMap_.clear();
+
+ // Number MachineInstrs and MachineBasicBlocks.
+ // Initialize MBB indexes to a sentinal.
+ MBB2IdxMap.resize(mf_->getNumBlockIDs(), std::make_pair(~0U,~0U));
+
+ unsigned MIIndex = 0;
+ for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
+ MBB != E; ++MBB) {
+ unsigned StartIdx = MIIndex;
+
+ for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
+ I != E; ++I) {
+ bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
+ assert(inserted && "multiple MachineInstr -> index mappings");
+ i2miMap_.push_back(I);
+ MIIndex += InstrSlots::NUM;
+ }
+
+ if (StartIdx == MIIndex) {
+ // Empty MBB
+ MIIndex += InstrSlots::NUM;
+ i2miMap_.push_back(0);
+ }
+ // Set the MBB2IdxMap entry for this MBB.
+ MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
+ Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
+ }
+ std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
+
+ if (!OldI2MI.empty())
+ for (iterator I = begin(), E = end(); I != E; ++I)
+ for (LiveInterval::iterator LI = I->second.begin(), LE = I->second.end();
+ LI != LE; ++LI) {
+
+ // Remap the start index of the live range to the corresponding new
+ // number, or our best guess at what it _should_ correspond to if the
+ // original instruction has been erased. This is either the following
+ // instruction or its predecessor.
+ unsigned offset = LI->start % InstrSlots::NUM;
+ if (OldI2MI[LI->start / InstrSlots::NUM])
+ LI->start = mi2iMap_[OldI2MI[LI->start / InstrSlots::NUM]] + offset;
+ else {
+ unsigned i = 0;
+ MachineInstr* newInstr = 0;
+ do {
+ newInstr = OldI2MI[LI->start / InstrSlots::NUM + i];
+ i++;
+ } while (!newInstr);
+
+ if (mi2iMap_[newInstr] ==
+ MBB2IdxMap[newInstr->getParent()->getNumber()].first)
+ LI->start = mi2iMap_[newInstr];
+ else
+ LI->start = mi2iMap_[newInstr] - InstrSlots::NUM + offset;
+ }
+
+ // Remap the ending index in the same way that we remapped the start,
+ // except for the final step where we always map to the immediately
+ // following instruction.
+ if (LI->end / InstrSlots::NUM < OldI2MI.size()) {
+ offset = LI->end % InstrSlots::NUM;
+ if (OldI2MI[LI->end / InstrSlots::NUM])
+ LI->end = mi2iMap_[OldI2MI[LI->end / InstrSlots::NUM]] + offset;
+ else {
+ unsigned i = 0;
+ MachineInstr* newInstr = 0;
+ do {
+ newInstr = OldI2MI[LI->end / InstrSlots::NUM + i];
+ i++;
+ } while (!newInstr);
+
+ LI->end = mi2iMap_[newInstr];
+ }
+ } else {
+ LI->end = i2miMap_.size() * InstrSlots::NUM;
+ }
+
+ // Remap the VNInfo def index, which works the same as the
+ // start indices above.
+ VNInfo* vni = LI->valno;
+ offset = vni->def % InstrSlots::NUM;
+ if (OldI2MI[vni->def / InstrSlots::NUM])
+ vni->def = mi2iMap_[OldI2MI[vni->def / InstrSlots::NUM]] + offset;
+ else {
+ unsigned i = 0;
+ MachineInstr* newInstr = 0;
+ do {
+ newInstr = OldI2MI[vni->def / InstrSlots::NUM + i];
+ i++;
+ } while (!newInstr);
+
+ if (mi2iMap_[newInstr] ==
+ MBB2IdxMap[newInstr->getParent()->getNumber()].first)
+ vni->def = mi2iMap_[newInstr];
+ else
+ vni->def = mi2iMap_[newInstr] - InstrSlots::NUM + offset;
+ }
+
+ // Remap the VNInfo kill indices, which works the same as
+ // the end indices above.
+ for (size_t i = 0; i < vni->kills.size(); ++i) {
+ offset = vni->kills[i] % InstrSlots::NUM;
+ if (OldI2MI[vni->kills[i] / InstrSlots::NUM])
+ vni->kills[i] = mi2iMap_[OldI2MI[vni->kills[i] / InstrSlots::NUM]] +
+ offset;
+ else {
+ unsigned e = 0;
+ MachineInstr* newInstr = 0;
+ do {
+ newInstr = OldI2MI[vni->kills[i] / InstrSlots::NUM + e];
+ e++;
+ } while (!newInstr);
+
+ vni->kills[i] = mi2iMap_[newInstr];
+ }
+ }
+ }
}
-
/// runOnMachineFunction - Register allocate the whole function
///
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
+ mri_ = &mf_->getRegInfo();
tm_ = &fn.getTarget();
- mri_ = tm_->getRegisterInfo();
+ tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
lv_ = &getAnalysis<LiveVariables>();
- allocatableRegs_ = mri_->getAllocatableSet(fn);
- r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
-
- // If this function has any live ins, insert a dummy instruction at the
- // beginning of the function that we will pretend "defines" the values. This
- // is to make the interval analysis simpler by providing a number.
- if (fn.livein_begin() != fn.livein_end()) {
- unsigned FirstLiveIn = fn.livein_begin()->first;
-
- // Find a reg class that contains this live in.
- const TargetRegisterClass *RC = 0;
- for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
- E = mri_->regclass_end(); RCI != E; ++RCI)
- if ((*RCI)->contains(FirstLiveIn)) {
- RC = *RCI;
- break;
- }
-
- MachineInstr *OldFirstMI = fn.begin()->begin();
- mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
- FirstLiveIn, FirstLiveIn, RC);
- assert(OldFirstMI != fn.begin()->begin() &&
- "copyRetToReg didn't insert anything!");
- }
-
- // number MachineInstrs
- unsigned miIndex = 0;
- for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
- mbb != mbbEnd; ++mbb)
- for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
- mi != miEnd; ++mi) {
- bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
- assert(inserted && "multiple MachineInstr -> index mappings");
- i2miMap_.push_back(mi);
- miIndex += InstrSlots::NUM;
- }
-
- // Note intervals due to live-in values.
- if (fn.livein_begin() != fn.livein_end()) {
- MachineBasicBlock *Entry = fn.begin();
- for (MachineFunction::livein_iterator I = fn.livein_begin(),
- E = fn.livein_end(); I != E; ++I) {
- handlePhysicalRegisterDef(Entry, Entry->begin(),
- getOrCreateInterval(I->first), 0, 0, true);
- for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
- handlePhysicalRegisterDef(Entry, Entry->begin(),
- getOrCreateInterval(*AS), 0, 0, true);
- }
- }
+ allocatableRegs_ = tri_->getAllocatableSet(fn);
+ computeNumbering();
computeIntervals();
numIntervals += getNumIntervals();
- DEBUG(std::cerr << "********** INTERVALS **********\n";
- for (iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(std::cerr, mri_);
- std::cerr << "\n";
- });
-
- // join intervals if requested
- if (EnableJoining) joinIntervals();
-
- numIntervalsAfter += getNumIntervals();
-
- // perform a final pass over the instructions and compute spill
- // weights, coalesce virtual registers and remove identity moves
- const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
-
- for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
- mbbi != mbbe; ++mbbi) {
- MachineBasicBlock* mbb = mbbi;
- unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
-
- for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
- mii != mie; ) {
- // if the move will be an identity move delete it
- unsigned srcReg, dstReg, RegRep;
- if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
- (RegRep = rep(srcReg)) == rep(dstReg)) {
- // remove from def list
- LiveInterval &interval = getOrCreateInterval(RegRep);
- // remove index -> MachineInstr and
- // MachineInstr -> index mappings
- Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
- if (mi2i != mi2iMap_.end()) {
- i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
- mi2iMap_.erase(mi2i);
- }
- mii = mbbi->erase(mii);
- ++numPeep;
- }
- else {
- for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
- const MachineOperand& mop = mii->getOperand(i);
- if (mop.isRegister() && mop.getReg() &&
- MRegisterInfo::isVirtualRegister(mop.getReg())) {
- // replace register with representative register
- unsigned reg = rep(mop.getReg());
- mii->getOperand(i).setReg(reg);
-
- LiveInterval &RegInt = getInterval(reg);
- RegInt.weight +=
- (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
- }
- }
- ++mii;
- }
- }
- }
-
+ DOUT << "********** INTERVALS **********\n";
for (iterator I = begin(), E = end(); I != E; ++I) {
- LiveInterval &li = I->second;
- if (MRegisterInfo::isVirtualRegister(li.reg))
- // If the live interval legnth is essentially zero, i.e. in every live
- // range the use follows def immediately, it doesn't make sense to spill
- // it and hope it will be easier to allocate for this li.
- if (isZeroLengthInterval(&li))
- li.weight = float(HUGE_VAL);
+ I->second.print(DOUT, tri_);
+ DOUT << "\n";
}
+ numIntervalsAfter += getNumIntervals();
DEBUG(dump());
return true;
}
void LiveIntervals::print(std::ostream &O, const Module* ) const {
O << "********** INTERVALS **********\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
- I->second.print(std::cerr, mri_);
- std::cerr << "\n";
+ I->second.print(O, tri_);
+ O << "\n";
}
O << "********** MACHINEINSTRS **********\n";
}
}
-std::vector<LiveInterval*> LiveIntervals::
-addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
- // since this is called after the analysis is done we don't know if
- // LiveVariables is available
- lv_ = getAnalysisToUpdate<LiveVariables>();
-
- std::vector<LiveInterval*> added;
-
- assert(li.weight != HUGE_VAL &&
- "attempt to spill already spilled interval!");
-
- DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
- << li << '\n');
-
- const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
-
+/// conflictsWithPhysRegDef - Returns true if the specified register
+/// is defined during the duration of the specified interval.
+bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
+ VirtRegMap &vrm, unsigned reg) {
for (LiveInterval::Ranges::const_iterator
- i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
- unsigned index = getBaseIndex(i->start);
- unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
- for (; index != end; index += InstrSlots::NUM) {
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ for (unsigned index = getBaseIndex(I->start),
+ end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end;
+ index += InstrSlots::NUM) {
// skip deleted instructions
while (index != end && !getInstructionFromIndex(index))
index += InstrSlots::NUM;
if (index == end) break;
MachineInstr *MI = getInstructionFromIndex(index);
-
- // NewRegLiveIn - This instruction might have multiple uses of the spilled
- // register. In this case, for the first use, keep track of the new vreg
- // that we reload it into. If we see a second use, reuse this vreg
- // instead of creating live ranges for two reloads.
- unsigned NewRegLiveIn = 0;
-
- for_operand:
+ unsigned SrcReg, DstReg;
+ if (tii_->isMoveInstr(*MI, SrcReg, DstReg))
+ if (SrcReg == li.reg || DstReg == li.reg)
+ continue;
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
- if (mop.isRegister() && mop.getReg() == li.reg) {
- if (NewRegLiveIn && mop.isUse()) {
- // We already emitted a reload of this value, reuse it for
- // subsequent operands.
- MI->getOperand(i).setReg(NewRegLiveIn);
- DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
- << " for operand #" << i << '\n');
- } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
- // Attempt to fold the memory reference into the instruction. If we
- // can do this, we don't need to insert spill code.
- if (lv_)
- lv_->instructionChanged(MI, fmi);
- MachineBasicBlock &MBB = *MI->getParent();
- vrm.virtFolded(li.reg, MI, i, fmi);
- mi2iMap_.erase(MI);
- i2miMap_[index/InstrSlots::NUM] = fmi;
- mi2iMap_[fmi] = index;
- MI = MBB.insert(MBB.erase(MI), fmi);
- ++numFolded;
- // Folding the load/store can completely change the instruction in
- // unpredictable ways, rescan it from the beginning.
- goto for_operand;
- } else {
- // This is tricky. We need to add information in the interval about
- // the spill code so we have to use our extra load/store slots.
- //
- // If we have a use we are going to have a load so we start the
- // interval from the load slot onwards. Otherwise we start from the
- // def slot.
- unsigned start = (mop.isUse() ?
- getLoadIndex(index) :
- getDefIndex(index));
- // If we have a def we are going to have a store right after it so
- // we end the interval after the use of the next
- // instruction. Otherwise we end after the use of this instruction.
- unsigned end = 1 + (mop.isDef() ?
- getStoreIndex(index) :
- getUseIndex(index));
-
- // create a new register for this spill
- NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
- MI->getOperand(i).setReg(NewRegLiveIn);
- vrm.grow();
- vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
- LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
- assert(nI.empty());
-
- // the spill weight is now infinity as it
- // cannot be spilled again
- nI.weight = float(HUGE_VAL);
- LiveRange LR(start, end, nI.getNextValue(~0U));
- DEBUG(std::cerr << " +" << LR);
- nI.addRange(LR);
- added.push_back(&nI);
-
- // update live variables if it is available
- if (lv_)
- lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
-
- // If this is a live in, reuse it for subsequent live-ins. If it's
- // a def, we can't do this.
- if (!mop.isUse()) NewRegLiveIn = 0;
-
- DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
- }
+ if (!mop.isRegister())
+ continue;
+ unsigned PhysReg = mop.getReg();
+ if (PhysReg == 0 || PhysReg == li.reg)
+ continue;
+ if (TargetRegisterInfo::isVirtualRegister(PhysReg)) {
+ if (!vrm.hasPhys(PhysReg))
+ continue;
+ PhysReg = vrm.getPhys(PhysReg);
}
+ if (PhysReg && tri_->regsOverlap(PhysReg, reg))
+ return true;
}
}
}
- return added;
+ return false;
}
void LiveIntervals::printRegName(unsigned reg) const {
- if (MRegisterInfo::isPhysicalRegister(reg))
- std::cerr << mri_->getName(reg);
+ if (TargetRegisterInfo::isPhysicalRegister(reg))
+ cerr << tri_->getName(reg);
else
- std::cerr << "%reg" << reg;
+ cerr << "%reg" << reg;
}
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
+ unsigned MIIdx,
LiveInterval &interval) {
- DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
+ DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
+ if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ DOUT << "is a implicit_def\n";
+ return;
+ }
+
// Virtual registers may be defined multiple times (due to phi
// elimination and 2-addr elimination). Much of what we do only has to be
// done once for the vreg. We use an empty interval to detect the first
// time we see a vreg.
if (interval.empty()) {
// Get the Idx of the defining instructions.
- unsigned defIndex = getDefIndex(getInstructionIndex(mi));
-
- unsigned ValNum = interval.getNextValue(defIndex);
- assert(ValNum == 0 && "First value in interval is not 0?");
- ValNum = 0; // Clue in the optimizer.
+ unsigned defIndex = getDefIndex(MIIdx);
+ VNInfo *ValNo;
+ MachineInstr *CopyMI = NULL;
+ unsigned SrcReg, DstReg;
+ if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+ mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ tii_->isMoveInstr(*mi, SrcReg, DstReg))
+ CopyMI = mi;
+ ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
+
+ assert(ValNo->id == 0 && "First value in interval is not 0?");
// Loop over all of the blocks that the vreg is defined in. There are
// two cases we have to handle here. The most common case is a vreg
// If the kill happens after the definition, we have an intra-block
// live range.
if (killIdx > defIndex) {
- assert(vi.AliveBlocks.empty() &&
+ assert(vi.AliveBlocks.none() &&
"Shouldn't be alive across any blocks!");
- LiveRange LR(defIndex, killIdx, ValNum);
+ LiveRange LR(defIndex, killIdx, ValNo);
interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR << "\n");
+ DOUT << " +" << LR << "\n";
+ interval.addKill(ValNo, killIdx);
return;
}
}
// range that goes from this definition to the end of the defining block.
LiveRange NewLR(defIndex,
getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
- ValNum);
- DEBUG(std::cerr << " +" << NewLR);
+ ValNo);
+ DOUT << " +" << NewLR;
interval.addRange(NewLR);
// Iterate over all of the blocks that the variable is completely
// live interval.
for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
if (vi.AliveBlocks[i]) {
- MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
- if (!mbb->empty()) {
- LiveRange LR(getInstructionIndex(&mbb->front()),
- getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
- ValNum);
- interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR);
- }
+ LiveRange LR(getMBBStartIdx(i),
+ getMBBEndIdx(i)+1, // MBB ends at -1.
+ ValNo);
+ interval.addRange(LR);
+ DOUT << " +" << LR;
}
}
// block to the 'use' slot of the killing instruction.
for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
MachineInstr *Kill = vi.Kills[i];
- LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
- getUseIndex(getInstructionIndex(Kill))+1,
- ValNum);
+ unsigned killIdx = getUseIndex(getInstructionIndex(Kill))+1;
+ LiveRange LR(getMBBStartIdx(Kill->getParent()),
+ killIdx, ValNo);
interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR);
+ interval.addKill(ValNo, killIdx);
+ DOUT << " +" << LR;
}
} else {
// If this is the second time we see a virtual register definition, it
// must be due to phi elimination or two addr elimination. If this is
- // the result of two address elimination, then the vreg is the first
- // operand, and is a def-and-use.
- if (mi->getOperand(0).isRegister() &&
- mi->getOperand(0).getReg() == interval.reg &&
- mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
+ // the result of two address elimination, then the vreg is one of the
+ // def-and-use register operand.
+ if (mi->isRegReDefinedByTwoAddr(interval.reg)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
// need to take the LiveRegion that defines this register and split it
// into two values.
- unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
- unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
+ assert(interval.containsOneValue());
+ unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def);
+ unsigned RedefIndex = getDefIndex(MIIdx);
+
+ const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
+ VNInfo *OldValNo = OldLR->valno;
// Delete the initial value, which should be short and continuous,
// because the 2-addr copy must be in the same MBB as the redef.
// that at this point, there should be exactly one value number in it.
assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
- // The new value number is defined by the instruction we claimed defined
- // value #0.
- unsigned ValNo = interval.getNextValue(DefIndex);
+ // The new value number (#1) is defined by the instruction we claimed
+ // defined value #0.
+ VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->copy,
+ VNInfoAllocator);
- // Value#1 is now defined by the 2-addr instruction.
- interval.setInstDefiningValNum(0, RedefIndex);
+ // Value#0 is now defined by the 2-addr instruction.
+ OldValNo->def = RedefIndex;
+ OldValNo->copy = 0;
// Add the new live interval which replaces the range for the input copy.
LiveRange LR(DefIndex, RedefIndex, ValNo);
- DEBUG(std::cerr << " replace range with " << LR);
+ DOUT << " replace range with " << LR;
interval.addRange(LR);
+ interval.addKill(ValNo, RedefIndex);
// If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot.
- if (lv_->RegisterDefIsDead(mi, interval.reg))
- interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
+ if (mi->registerDefIsDead(interval.reg, tri_))
+ interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
- DEBUG(std::cerr << "RESULT: " << interval);
+ DOUT << " RESULT: ";
+ interval.print(DOUT, tri_);
} else {
// Otherwise, this must be because of phi elimination. If this is the
"PHI elimination vreg should have one kill, the PHI itself!");
// Remove the old range that we now know has an incorrect number.
+ VNInfo *VNI = interval.getValNumInfo(0);
MachineInstr *Killer = vi.Kills[0];
- unsigned Start = getInstructionIndex(Killer->getParent()->begin());
+ unsigned Start = getMBBStartIdx(Killer->getParent());
unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
- DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
- << interval << "\n");
+ DOUT << " Removing [" << Start << "," << End << "] from: ";
+ interval.print(DOUT, tri_); DOUT << "\n";
interval.removeRange(Start, End);
- DEBUG(std::cerr << "RESULT: " << interval);
+ VNI->hasPHIKill = true;
+ DOUT << " RESULT: "; interval.print(DOUT, tri_);
// Replace the interval with one of a NEW value number. Note that this
// value number isn't actually defined by an instruction, weird huh? :)
- LiveRange LR(Start, End, interval.getNextValue(~0U));
- DEBUG(std::cerr << " replace range with " << LR);
+ LiveRange LR(Start, End, interval.getNextValue(~0, 0, VNInfoAllocator));
+ DOUT << " replace range with " << LR;
interval.addRange(LR);
- DEBUG(std::cerr << "RESULT: " << interval);
+ interval.addKill(LR.valno, End);
+ DOUT << " RESULT: "; interval.print(DOUT, tri_);
}
// In the case of PHI elimination, each variable definition is only
// live until the end of the block. We've already taken care of the
// rest of the live range.
- unsigned defIndex = getDefIndex(getInstructionIndex(mi));
- LiveRange LR(defIndex,
- getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
- interval.getNextValue(defIndex));
+ unsigned defIndex = getDefIndex(MIIdx);
+
+ VNInfo *ValNo;
+ MachineInstr *CopyMI = NULL;
+ unsigned SrcReg, DstReg;
+ if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+ mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ tii_->isMoveInstr(*mi, SrcReg, DstReg))
+ CopyMI = mi;
+ ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
+
+ unsigned killIndex = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
+ LiveRange LR(defIndex, killIndex, ValNo);
interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR);
+ interval.addKill(ValNo, killIndex);
+ ValNo->hasPHIKill = true;
+ DOUT << " +" << LR;
}
}
- DEBUG(std::cerr << '\n');
+ DOUT << '\n';
}
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
- LiveInterval& interval,
- unsigned SrcReg, unsigned DestReg,
- bool isLiveIn) {
+ unsigned MIIdx,
+ LiveInterval &interval,
+ MachineInstr *CopyMI) {
// A physical register cannot be live across basic block, so its
// lifetime must end somewhere in its defining basic block.
- DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
- typedef LiveVariables::killed_iterator KillIter;
+ DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
- unsigned baseIndex = getInstructionIndex(mi);
+ unsigned baseIndex = MIIdx;
unsigned start = getDefIndex(baseIndex);
unsigned end = start;
// If it is not used after definition, it is considered dead at
// the instruction defining it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
- if (lv_->RegisterDefIsDead(mi, interval.reg)) {
- DEBUG(std::cerr << " dead");
+ if (mi->registerDefIsDead(interval.reg, tri_)) {
+ DOUT << " dead";
end = getDefIndex(start) + 1;
goto exit;
}
// [defSlot(def), useSlot(kill)+1)
while (++mi != MBB->end()) {
baseIndex += InstrSlots::NUM;
- if (lv_->KillsRegister(mi, interval.reg)) {
- DEBUG(std::cerr << " killed");
+ if (mi->killsRegister(interval.reg, tri_)) {
+ DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
goto exit;
+ } else if (mi->modifiesRegister(interval.reg, tri_)) {
+ // Another instruction redefines the register before it is ever read.
+ // Then the register is essentially dead at the instruction that defines
+ // it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ DOUT << " dead";
+ end = getDefIndex(start) + 1;
+ goto exit;
}
}
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
// and never used.
- assert(isLiveIn && "physreg was not killed in defining block!");
+ assert(!CopyMI && "physreg was not killed in defining block!");
end = getDefIndex(start) + 1; // It's dead.
exit:
assert(start < end && "did not find end of interval?");
- // Finally, if this is defining a new range for the physical register, and if
- // that physreg is just a copy from a vreg, and if THAT vreg was a copy from
- // the physreg, then the new fragment has the same value as the one copied
- // into the vreg.
- if (interval.reg == DestReg && !interval.empty() &&
- MRegisterInfo::isVirtualRegister(SrcReg)) {
-
- // Get the live interval for the vreg, see if it is defined by a copy.
- LiveInterval &SrcInterval = getOrCreateInterval(SrcReg);
-
- if (SrcInterval.containsOneValue()) {
- assert(!SrcInterval.empty() && "Can't contain a value and be empty!");
-
- // Get the first index of the first range. Though the interval may have
- // multiple liveranges in it, we only check the first.
- unsigned StartIdx = SrcInterval.begin()->start;
- MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx);
-
- // Check to see if the vreg was defined by a copy instruction, and that
- // the source was this physreg.
- unsigned VRegSrcSrc, VRegSrcDest;
- if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) &&
- SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) {
- // Okay, now we know that the vreg was defined by a copy from this
- // physreg. Find the value number being copied and use it as the value
- // for this range.
- const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1);
- if (DefRange) {
- LiveRange LR(start, end, DefRange->ValId);
- interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR << '\n');
- return;
- }
- }
- }
- }
-
- LiveRange LR(start, end, interval.getNextValue(start));
+ // Already exists? Extend old live interval.
+ LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
+ VNInfo *ValNo = (OldLR != interval.end())
+ ? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
+ LiveRange LR(start, end, ValNo);
interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR << '\n');
+ interval.addKill(LR.valno, end);
+ DOUT << " +" << LR << '\n';
}
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
+ unsigned MIIdx,
unsigned reg) {
- if (MRegisterInfo::isVirtualRegister(reg))
- handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
+ if (TargetRegisterInfo::isVirtualRegister(reg))
+ handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
else if (allocatableRegs_[reg]) {
- unsigned SrcReg = 0, DestReg = 0;
- if (!tii_->isMoveInstr(*MI, SrcReg, DestReg))
- SrcReg = DestReg = 0;
+ MachineInstr *CopyMI = NULL;
+ unsigned SrcReg, DstReg;
+ if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+ MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ tii_->isMoveInstr(*MI, SrcReg, DstReg))
+ CopyMI = MI;
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI);
+ // Def of a register also defines its sub-registers.
+ for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
+ // If MI also modifies the sub-register explicitly, avoid processing it
+ // more than once. Do not pass in TRI here so it checks for exact match.
+ if (!MI->modifiesRegister(*AS))
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
+ }
+}
+
+void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
+ unsigned MIIdx,
+ LiveInterval &interval, bool isAlias) {
+ DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
+
+ // Look for kills, if it reaches a def before it's killed, then it shouldn't
+ // be considered a livein.
+ MachineBasicBlock::iterator mi = MBB->begin();
+ unsigned baseIndex = MIIdx;
+ unsigned start = baseIndex;
+ unsigned end = start;
+ while (mi != MBB->end()) {
+ if (mi->killsRegister(interval.reg, tri_)) {
+ DOUT << " killed";
+ end = getUseIndex(baseIndex) + 1;
+ goto exit;
+ } else if (mi->modifiesRegister(interval.reg, tri_)) {
+ // Another instruction redefines the register before it is ever read.
+ // Then the register is essentially dead at the instruction that defines
+ // it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ DOUT << " dead";
+ end = getDefIndex(start) + 1;
+ goto exit;
+ }
- handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg),
- SrcReg, DestReg);
- for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
- handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS),
- SrcReg, DestReg);
+ baseIndex += InstrSlots::NUM;
+ ++mi;
}
+
+exit:
+ // Live-in register might not be used at all.
+ if (end == MIIdx) {
+ if (isAlias) {
+ DOUT << " dead";
+ end = getDefIndex(MIIdx) + 1;
+ } else {
+ DOUT << " live through";
+ end = baseIndex;
+ }
+ }
+
+ LiveRange LR(start, end, interval.getNextValue(start, 0, VNInfoAllocator));
+ interval.addRange(LR);
+ interval.addKill(LR.valno, end);
+ DOUT << " +" << LR << '\n';
}
/// computeIntervals - computes the live intervals for virtual
/// registers. for some ordering of the machine instructions [1,N] a
/// live interval is an interval [i, j) where 1 <= i <= j < N for
/// which a variable is live
-void LiveIntervals::computeIntervals()
-{
- DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
- DEBUG(std::cerr << "********** Function: "
- << ((Value*)mf_->getFunction())->getName() << '\n');
- bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
-
- for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
- I != E; ++I) {
- MachineBasicBlock* mbb = I;
- DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
-
- MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
- if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
- for (; mi != miEnd; ++mi) {
- const TargetInstrDescriptor& tid =
- tm_->getInstrInfo()->get(mi->getOpcode());
- DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
-
- // handle implicit defs
- if (tid.ImplicitDefs) {
- for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
- handleRegisterDef(mbb, mi, *id);
- }
+void LiveIntervals::computeIntervals() {
+ DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
+ << "********** Function: "
+ << ((Value*)mf_->getFunction())->getName() << '\n';
+ // Track the index of the current machine instr.
+ unsigned MIIndex = 0;
+ for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
+ MBBI != E; ++MBBI) {
+ MachineBasicBlock *MBB = MBBI;
+ DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
+
+ MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
+
+ // Create intervals for live-ins to this BB first.
+ for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
+ LE = MBB->livein_end(); LI != LE; ++LI) {
+ handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
+ // Multiple live-ins can alias the same register.
+ for (const unsigned* AS = tri_->getSubRegisters(*LI); *AS; ++AS)
+ if (!hasInterval(*AS))
+ handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
+ true);
+ }
+
+ for (; MI != miEnd; ++MI) {
+ DOUT << MIIndex << "\t" << *MI;
- // handle explicit defs
- for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = mi->getOperand(i);
+ // Handle defs.
+ for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
- if (mop.isRegister() && mop.getReg() && mop.isDef())
- handleRegisterDef(mbb, mi, mop.getReg());
+ if (MO.isRegister() && MO.getReg() && MO.isDef())
+ handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
}
+
+ MIIndex += InstrSlots::NUM;
}
+
+ if (MBB->begin() == miEnd) MIIndex += InstrSlots::NUM; // Empty MBB
}
}
-/// IntA is defined as a copy from IntB and we know it only has one value
-/// number. If all of the places that IntA and IntB overlap are defined by
-/// copies from IntA to IntB, we know that these two ranges can really be
-/// merged if we adjust the value numbers. If it is safe, adjust the value
-/// numbers and return true, allowing coalescing to occur.
-bool LiveIntervals::
-AdjustIfAllOverlappingRangesAreCopiesFrom(LiveInterval &IntA,
- LiveInterval &IntB,
- unsigned CopyIdx) {
- std::vector<LiveRange*> Ranges;
- IntA.getOverlapingRanges(IntB, CopyIdx, Ranges);
-
- assert(!Ranges.empty() && "Why didn't we do a simple join of this?");
-
- unsigned IntBRep = rep(IntB.reg);
-
- // Check to see if all of the overlaps (entries in Ranges) are defined by a
- // copy from IntA. If not, exit.
- for (unsigned i = 0, e = Ranges.size(); i != e; ++i) {
- unsigned Idx = Ranges[i]->start;
- MachineInstr *MI = getInstructionFromIndex(Idx);
- unsigned SrcReg, DestReg;
- if (!tii_->isMoveInstr(*MI, SrcReg, DestReg)) return false;
-
- // If this copy isn't actually defining this range, it must be a live
- // range spanning basic blocks or something.
- if (rep(DestReg) != rep(IntA.reg)) return false;
-
- // Check to see if this is coming from IntB. If not, bail out.
- if (rep(SrcReg) != IntBRep) return false;
+bool LiveIntervals::findLiveInMBBs(const LiveRange &LR,
+ SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), LR.start);
+
+ bool ResVal = false;
+ while (I != Idx2MBBMap.end()) {
+ if (LR.end <= I->first)
+ break;
+ MBBs.push_back(I->second);
+ ResVal = true;
+ ++I;
}
+ return ResVal;
+}
- // Okay, we can change this one. Get the IntB value number that IntA is
- // copied from.
- unsigned ActualValNo = IntA.getLiveRangeContaining(CopyIdx-1)->ValId;
-
- // Change all of the value numbers to the same as what we IntA is copied from.
- for (unsigned i = 0, e = Ranges.size(); i != e; ++i)
- Ranges[i]->ValId = ActualValNo;
-
- return true;
+
+LiveInterval LiveIntervals::createInterval(unsigned reg) {
+ float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
+ HUGE_VALF : 0.0F;
+ return LiveInterval(reg, Weight);
}
-void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
- DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
+/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
+/// copy field and returns the source register that defines it.
+unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
+ if (!VNI->copy)
+ return 0;
+
+ if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
+ return VNI->copy->getOperand(1).getReg();
+ if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
+ return VNI->copy->getOperand(2).getReg();
+ unsigned SrcReg, DstReg;
+ if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg))
+ return SrcReg;
+ assert(0 && "Unrecognized copy instruction!");
+ return 0;
+}
- for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
- mi != mie; ++mi) {
- DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
+//===----------------------------------------------------------------------===//
+// Register allocator hooks.
+//
- // we only join virtual registers with allocatable
- // physical registers since we do not have liveness information
- // on not allocatable physical registers
- unsigned SrcReg, DestReg;
- if (tii_->isMoveInstr(*mi, SrcReg, DestReg) &&
- (MRegisterInfo::isVirtualRegister(SrcReg) || allocatableRegs_[SrcReg])&&
- (MRegisterInfo::isVirtualRegister(DestReg)||allocatableRegs_[DestReg])){
+/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
+/// allow one) virtual register operand, then its uses are implicitly using
+/// the register. Returns the virtual register.
+unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
+ MachineInstr *MI) const {
+ unsigned RegOp = 0;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isRegister() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == 0 || Reg == li.reg)
+ continue;
+ // FIXME: For now, only remat MI with at most one register operand.
+ assert(!RegOp &&
+ "Can't rematerialize instruction with multiple register operand!");
+ RegOp = MO.getReg();
+ break;
+ }
+ return RegOp;
+}
- // Get representative registers.
- SrcReg = rep(SrcReg);
- DestReg = rep(DestReg);
+/// isValNoAvailableAt - Return true if the val# of the specified interval
+/// which reaches the given instruction also reaches the specified use index.
+bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
+ unsigned UseIdx) const {
+ unsigned Index = getInstructionIndex(MI);
+ VNInfo *ValNo = li.FindLiveRangeContaining(Index)->valno;
+ LiveInterval::const_iterator UI = li.FindLiveRangeContaining(UseIdx);
+ return UI != li.end() && UI->valno == ValNo;
+}
- // If they are already joined we continue.
- if (SrcReg == DestReg)
- continue;
+/// isReMaterializable - Returns true if the definition MI of the specified
+/// val# of the specified interval is re-materializable.
+bool LiveIntervals::isReMaterializable(const LiveInterval &li,
+ const VNInfo *ValNo, MachineInstr *MI,
+ bool &isLoad) {
+ if (DisableReMat)
+ return false;
+
+ isLoad = false;
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ return true;
+
+ int FrameIdx = 0;
+ if (tii_->isLoadFromStackSlot(MI, FrameIdx) &&
+ mf_->getFrameInfo()->isImmutableObjectIndex(FrameIdx))
+ // FIXME: Let target specific isReallyTriviallyReMaterializable determines
+ // this but remember this is not safe to fold into a two-address
+ // instruction.
+ // This is a load from fixed stack slot. It can be rematerialized.
+ return true;
+
+ if (tii_->isTriviallyReMaterializable(MI)) {
+ const TargetInstrDesc &TID = MI->getDesc();
+ isLoad = TID.isSimpleLoad();
+
+ unsigned ImpUse = getReMatImplicitUse(li, MI);
+ if (ImpUse) {
+ const LiveInterval &ImpLi = getInterval(ImpUse);
+ for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg),
+ re = mri_->use_end(); ri != re; ++ri) {
+ MachineInstr *UseMI = &*ri;
+ unsigned UseIdx = getInstructionIndex(UseMI);
+ if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo)
+ continue;
+ if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
+ return false;
+ }
+ }
+ return true;
+ }
- // If they are both physical registers, we cannot join them.
- if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
- MRegisterInfo::isPhysicalRegister(DestReg))
- continue;
+ return false;
+}
+
+/// isReMaterializable - Returns true if every definition of MI of every
+/// val# of the specified interval is re-materializable.
+bool LiveIntervals::isReMaterializable(const LiveInterval &li, bool &isLoad) {
+ isLoad = false;
+ for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
+ i != e; ++i) {
+ const VNInfo *VNI = *i;
+ unsigned DefIdx = VNI->def;
+ if (DefIdx == ~1U)
+ continue; // Dead val#.
+ // Is the def for the val# rematerializable?
+ if (DefIdx == ~0u)
+ return false;
+ MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx);
+ bool DefIsLoad = false;
+ if (!ReMatDefMI ||
+ !isReMaterializable(li, VNI, ReMatDefMI, DefIsLoad))
+ return false;
+ isLoad |= DefIsLoad;
+ }
+ return true;
+}
- // If they are not of the same register class, we cannot join them.
- if (differingRegisterClasses(SrcReg, DestReg))
+/// FilterFoldedOps - Filter out two-address use operands. Return
+/// true if it finds any issue with the operands that ought to prevent
+/// folding.
+static bool FilterFoldedOps(MachineInstr *MI,
+ SmallVector<unsigned, 2> &Ops,
+ unsigned &MRInfo,
+ SmallVector<unsigned, 2> &FoldOps) {
+ const TargetInstrDesc &TID = MI->getDesc();
+
+ MRInfo = 0;
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+ unsigned OpIdx = Ops[i];
+ MachineOperand &MO = MI->getOperand(OpIdx);
+ // FIXME: fold subreg use.
+ if (MO.getSubReg())
+ return true;
+ if (MO.isDef())
+ MRInfo |= (unsigned)VirtRegMap::isMod;
+ else {
+ // Filter out two-address use operand(s).
+ if (!MO.isImplicit() &&
+ TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
+ MRInfo = VirtRegMap::isModRef;
continue;
+ }
+ MRInfo |= (unsigned)VirtRegMap::isRef;
+ }
+ FoldOps.push_back(OpIdx);
+ }
+ return false;
+}
+
+
+/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
+/// slot / to reg or any rematerialized load into ith operand of specified
+/// MI. If it is successul, MI is updated with the newly created MI and
+/// returns true.
+bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
+ VirtRegMap &vrm, MachineInstr *DefMI,
+ unsigned InstrIdx,
+ SmallVector<unsigned, 2> &Ops,
+ bool isSS, int Slot, unsigned Reg) {
+ // If it is an implicit def instruction, just delete it.
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ RemoveMachineInstrFromMaps(MI);
+ vrm.RemoveMachineInstrFromMaps(MI);
+ MI->eraseFromParent();
+ ++numFolds;
+ return true;
+ }
+
+ // Filter the list of operand indexes that are to be folded. Abort if
+ // any operand will prevent folding.
+ unsigned MRInfo = 0;
+ SmallVector<unsigned, 2> FoldOps;
+ if (FilterFoldedOps(MI, Ops, MRInfo, FoldOps))
+ return false;
+
+ // The only time it's safe to fold into a two address instruction is when
+ // it's folding reload and spill from / into a spill stack slot.
+ if (DefMI && (MRInfo & VirtRegMap::isMod))
+ return false;
+
+ MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(*mf_, MI, FoldOps, Slot)
+ : tii_->foldMemoryOperand(*mf_, MI, FoldOps, DefMI);
+ if (fmi) {
+ // Remember this instruction uses the spill slot.
+ if (isSS) vrm.addSpillSlotUse(Slot, fmi);
+
+ // Attempt to fold the memory reference into the instruction. If
+ // we can do this, we don't need to insert spill code.
+ if (lv_)
+ lv_->instructionChanged(MI, fmi);
+ else
+ fmi->copyKillDeadInfo(MI, tri_);
+ MachineBasicBlock &MBB = *MI->getParent();
+ if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
+ vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
+ vrm.transferSpillPts(MI, fmi);
+ vrm.transferRestorePts(MI, fmi);
+ vrm.transferEmergencySpills(MI, fmi);
+ mi2iMap_.erase(MI);
+ i2miMap_[InstrIdx /InstrSlots::NUM] = fmi;
+ mi2iMap_[fmi] = InstrIdx;
+ MI = MBB.insert(MBB.erase(MI), fmi);
+ ++numFolds;
+ return true;
+ }
+ return false;
+}
+
+/// canFoldMemoryOperand - Returns true if the specified load / store
+/// folding is possible.
+bool LiveIntervals::canFoldMemoryOperand(MachineInstr *MI,
+ SmallVector<unsigned, 2> &Ops,
+ bool ReMat) const {
+ // Filter the list of operand indexes that are to be folded. Abort if
+ // any operand will prevent folding.
+ unsigned MRInfo = 0;
+ SmallVector<unsigned, 2> FoldOps;
+ if (FilterFoldedOps(MI, Ops, MRInfo, FoldOps))
+ return false;
+
+ // It's only legal to remat for a use, not a def.
+ if (ReMat && (MRInfo & VirtRegMap::isMod))
+ return false;
+
+ return tii_->canFoldMemoryOperand(MI, FoldOps);
+}
+
+bool LiveIntervals::intervalIsInOneMBB(const LiveInterval &li) const {
+ SmallPtrSet<MachineBasicBlock*, 4> MBBs;
+ for (LiveInterval::Ranges::const_iterator
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ std::vector<IdxMBBPair>::const_iterator II =
+ std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), I->start);
+ if (II == Idx2MBBMap.end())
+ continue;
+ if (I->end > II->first) // crossing a MBB.
+ return false;
+ MBBs.insert(II->second);
+ if (MBBs.size() > 1)
+ return false;
+ }
+ return true;
+}
- LiveInterval &SrcInt = getInterval(SrcReg);
- LiveInterval &DestInt = getInterval(DestReg);
- assert(SrcInt.reg == SrcReg && DestInt.reg == DestReg &&
- "Register mapping is horribly broken!");
+/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
+/// interval on to-be re-materialized operands of MI) with new register.
+void LiveIntervals::rewriteImplicitOps(const LiveInterval &li,
+ MachineInstr *MI, unsigned NewVReg,
+ VirtRegMap &vrm) {
+ // There is an implicit use. That means one of the other operand is
+ // being remat'ed and the remat'ed instruction has li.reg as an
+ // use operand. Make sure we rewrite that as well.
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isRegister())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
+ continue;
+ if (!vrm.isReMaterialized(Reg))
+ continue;
+ MachineInstr *ReMatMI = vrm.getReMaterializedMI(Reg);
+ MachineOperand *UseMO = ReMatMI->findRegisterUseOperand(li.reg);
+ if (UseMO)
+ UseMO->setReg(NewVReg);
+ }
+}
+
+/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper functions
+/// for addIntervalsForSpills to rewrite uses / defs for the given live range.
+bool LiveIntervals::
+rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
+ bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
+ MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
+ unsigned Slot, int LdSlot,
+ bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
+ VirtRegMap &vrm,
+ const TargetRegisterClass* rc,
+ SmallVector<int, 4> &ReMatIds,
+ const MachineLoopInfo *loopInfo,
+ unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
+ std::map<unsigned,unsigned> &MBBVRegsMap,
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
+ MachineBasicBlock *MBB = MI->getParent();
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+ bool CanFold = false;
+ RestartInstruction:
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& mop = MI->getOperand(i);
+ if (!mop.isRegister())
+ continue;
+ unsigned Reg = mop.getReg();
+ unsigned RegI = Reg;
+ if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
+ continue;
+ if (Reg != li.reg)
+ continue;
+
+ bool TryFold = !DefIsReMat;
+ bool FoldSS = true; // Default behavior unless it's a remat.
+ int FoldSlot = Slot;
+ if (DefIsReMat) {
+ // If this is the rematerializable definition MI itself and
+ // all of its uses are rematerialized, simply delete it.
+ if (MI == ReMatOrigDefMI && CanDelete) {
+ DOUT << "\t\t\t\tErasing re-materlizable def: ";
+ DOUT << MI << '\n';
+ RemoveMachineInstrFromMaps(MI);
+ vrm.RemoveMachineInstrFromMaps(MI);
+ MI->eraseFromParent();
+ break;
+ }
- DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
- std::cerr << " and "; DestInt.print(std::cerr, mri_);
- std::cerr << ": ");
+ // If def for this use can't be rematerialized, then try folding.
+ // If def is rematerializable and it's a load, also try folding.
+ TryFold = !ReMatDefMI || (ReMatDefMI && (MI == ReMatOrigDefMI || isLoad));
+ if (isLoad) {
+ // Try fold loads (from stack slot, constant pool, etc.) into uses.
+ FoldSS = isLoadSS;
+ FoldSlot = LdSlot;
+ }
+ }
- // If two intervals contain a single value and are joined by a copy, it
- // does not matter if the intervals overlap, they can always be joined.
- bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
+ // Scan all of the operands of this instruction rewriting operands
+ // to use NewVReg instead of li.reg as appropriate. We do this for
+ // two reasons:
+ //
+ // 1. If the instr reads the same spilled vreg multiple times, we
+ // want to reuse the NewVReg.
+ // 2. If the instr is a two-addr instruction, we are required to
+ // keep the src/dst regs pinned.
+ //
+ // Keep track of whether we replace a use and/or def so that we can
+ // create the spill interval with the appropriate range.
+
+ HasUse = mop.isUse();
+ HasDef = mop.isDef();
+ SmallVector<unsigned, 2> Ops;
+ Ops.push_back(i);
+ for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
+ const MachineOperand &MOj = MI->getOperand(j);
+ if (!MOj.isRegister())
+ continue;
+ unsigned RegJ = MOj.getReg();
+ if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
+ continue;
+ if (RegJ == RegI) {
+ Ops.push_back(j);
+ HasUse |= MOj.isUse();
+ HasDef |= MOj.isDef();
+ }
+ }
- unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
-
- // If the intervals think that this is joinable, do so now.
- if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
- Joinable = true;
-
- // If DestInt is actually a copy from SrcInt (which we know) that is used
- // to define another value of SrcInt, we can change the other range of
- // SrcInt to be the value of the range that defines DestInt, allowing a
- // coalesce.
- if (!Joinable && DestInt.containsOneValue() &&
- AdjustIfAllOverlappingRangesAreCopiesFrom(SrcInt, DestInt, MIDefIdx))
- Joinable = true;
-
- if (!Joinable || overlapsAliases(&SrcInt, &DestInt)) {
- DEBUG(std::cerr << "Interference!\n");
+ // Update stack slot spill weight if we are splitting.
+ float Weight = getSpillWeight(HasDef, HasUse, loopDepth);
+ if (!TrySplit)
+ SSWeight += Weight;
+
+ if (!TryFold)
+ CanFold = false;
+ else {
+ // Do not fold load / store here if we are splitting. We'll find an
+ // optimal point to insert a load / store later.
+ if (!TrySplit) {
+ if (tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
+ Ops, FoldSS, FoldSlot, Reg)) {
+ // Folding the load/store can completely change the instruction in
+ // unpredictable ways, rescan it from the beginning.
+ HasUse = false;
+ HasDef = false;
+ CanFold = false;
+ if (isRemoved(MI)) {
+ SSWeight -= Weight;
+ break;
+ }
+ goto RestartInstruction;
+ }
} else {
- DestInt.join(SrcInt, MIDefIdx);
- DEBUG(std::cerr << "Joined. Result = " << DestInt << "\n");
+ // We'll try to fold it later if it's profitable.
+ CanFold = canFoldMemoryOperand(MI, Ops, DefIsReMat);
+ }
+ }
- if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
- r2iMap_.erase(SrcReg);
- r2rMap_[SrcReg] = DestReg;
+ // Create a new virtual register for the spill interval.
+ bool CreatedNewVReg = false;
+ if (NewVReg == 0) {
+ NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ CreatedNewVReg = true;
+ }
+ mop.setReg(NewVReg);
+ if (mop.isImplicit())
+ rewriteImplicitOps(li, MI, NewVReg, vrm);
+
+ // Reuse NewVReg for other reads.
+ for (unsigned j = 0, e = Ops.size(); j != e; ++j) {
+ MachineOperand &mopj = MI->getOperand(Ops[j]);
+ mopj.setReg(NewVReg);
+ if (mopj.isImplicit())
+ rewriteImplicitOps(li, MI, NewVReg, vrm);
+ }
+
+ if (CreatedNewVReg) {
+ if (DefIsReMat) {
+ vrm.setVirtIsReMaterialized(NewVReg, ReMatDefMI/*, CanDelete*/);
+ if (ReMatIds[VNI->id] == VirtRegMap::MAX_STACK_SLOT) {
+ // Each valnum may have its own remat id.
+ ReMatIds[VNI->id] = vrm.assignVirtReMatId(NewVReg);
} else {
- // Otherwise merge the data structures the other way so we don't lose
- // the physreg information.
- r2rMap_[DestReg] = SrcReg;
- DestInt.reg = SrcReg;
- SrcInt.swap(DestInt);
- r2iMap_.erase(DestReg);
+ vrm.assignVirtReMatId(NewVReg, ReMatIds[VNI->id]);
+ }
+ if (!CanDelete || (HasUse && HasDef)) {
+ // If this is a two-addr instruction then its use operands are
+ // rematerializable but its def is not. It should be assigned a
+ // stack slot.
+ vrm.assignVirt2StackSlot(NewVReg, Slot);
}
- ++numJoins;
+ } else {
+ vrm.assignVirt2StackSlot(NewVReg, Slot);
}
+ } else if (HasUse && HasDef &&
+ vrm.getStackSlot(NewVReg) == VirtRegMap::NO_STACK_SLOT) {
+ // If this interval hasn't been assigned a stack slot (because earlier
+ // def is a deleted remat def), do it now.
+ assert(Slot != VirtRegMap::NO_STACK_SLOT);
+ vrm.assignVirt2StackSlot(NewVReg, Slot);
}
+
+ // Re-matting an instruction with virtual register use. Add the
+ // register as an implicit use on the use MI.
+ if (DefIsReMat && ImpUse)
+ MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+
+ // create a new register interval for this spill / remat.
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+ if (CreatedNewVReg) {
+ NewLIs.push_back(&nI);
+ MBBVRegsMap.insert(std::make_pair(MI->getParent()->getNumber(), NewVReg));
+ if (TrySplit)
+ vrm.setIsSplitFromReg(NewVReg, li.reg);
+ }
+
+ if (HasUse) {
+ if (CreatedNewVReg) {
+ LiveRange LR(getLoadIndex(index), getUseIndex(index)+1,
+ nI.getNextValue(~0U, 0, VNInfoAllocator));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ } else {
+ // Extend the split live interval to this def / use.
+ unsigned End = getUseIndex(index)+1;
+ LiveRange LR(nI.ranges[nI.ranges.size()-1].end, End,
+ nI.getValNumInfo(nI.getNumValNums()-1));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ }
+ }
+ if (HasDef) {
+ LiveRange LR(getDefIndex(index), getStoreIndex(index),
+ nI.getNextValue(~0U, 0, VNInfoAllocator));
+ DOUT << " +" << LR;
+ nI.addRange(LR);
+ }
+
+ DOUT << "\t\t\t\tAdded new interval: ";
+ nI.print(DOUT, tri_);
+ DOUT << '\n';
}
+ return CanFold;
+}
+bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li,
+ const VNInfo *VNI,
+ MachineBasicBlock *MBB, unsigned Idx) const {
+ unsigned End = getMBBEndIdx(MBB);
+ for (unsigned j = 0, ee = VNI->kills.size(); j != ee; ++j) {
+ unsigned KillIdx = VNI->kills[j];
+ if (KillIdx > Idx && KillIdx < End)
+ return true;
+ }
+ return false;
}
+/// RewriteInfo - Keep track of machine instrs that will be rewritten
+/// during spilling.
namespace {
- // DepthMBBCompare - Comparison predicate that sort first based on the loop
- // depth of the basic block (the unsigned), and then on the MBB number.
- struct DepthMBBCompare {
- typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
- bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
- if (LHS.first > RHS.first) return true; // Deeper loops first
- return LHS.first == RHS.first &&
- LHS.second->getNumber() < RHS.second->getNumber();
+ struct RewriteInfo {
+ unsigned Index;
+ MachineInstr *MI;
+ bool HasUse;
+ bool HasDef;
+ RewriteInfo(unsigned i, MachineInstr *mi, bool u, bool d)
+ : Index(i), MI(mi), HasUse(u), HasDef(d) {}
+ };
+
+ struct RewriteInfoCompare {
+ bool operator()(const RewriteInfo &LHS, const RewriteInfo &RHS) const {
+ return LHS.Index < RHS.Index;
}
};
}
-void LiveIntervals::joinIntervals() {
- DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
+void LiveIntervals::
+rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
+ LiveInterval::Ranges::const_iterator &I,
+ MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
+ unsigned Slot, int LdSlot,
+ bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
+ VirtRegMap &vrm,
+ const TargetRegisterClass* rc,
+ SmallVector<int, 4> &ReMatIds,
+ const MachineLoopInfo *loopInfo,
+ BitVector &SpillMBBs,
+ std::map<unsigned, std::vector<SRInfo> > &SpillIdxes,
+ BitVector &RestoreMBBs,
+ std::map<unsigned, std::vector<SRInfo> > &RestoreIdxes,
+ std::map<unsigned,unsigned> &MBBVRegsMap,
+ std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
+ bool AllCanFold = true;
+ unsigned NewVReg = 0;
+ unsigned start = getBaseIndex(I->start);
+ unsigned end = getBaseIndex(I->end-1) + InstrSlots::NUM;
+
+ // First collect all the def / use in this live range that will be rewritten.
+ // Make sure they are sorted according to instruction index.
+ std::vector<RewriteInfo> RewriteMIs;
+ for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
+ re = mri_->reg_end(); ri != re; ) {
+ MachineInstr *MI = &*ri;
+ MachineOperand &O = ri.getOperand();
+ ++ri;
+ assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
+ unsigned index = getInstructionIndex(MI);
+ if (index < start || index >= end)
+ continue;
+ RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));
+ }
+ std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare());
+
+ unsigned ImpUse = DefIsReMat ? getReMatImplicitUse(li, ReMatDefMI) : 0;
+ // Now rewrite the defs and uses.
+ for (unsigned i = 0, e = RewriteMIs.size(); i != e; ) {
+ RewriteInfo &rwi = RewriteMIs[i];
+ ++i;
+ unsigned index = rwi.Index;
+ bool MIHasUse = rwi.HasUse;
+ bool MIHasDef = rwi.HasDef;
+ MachineInstr *MI = rwi.MI;
+ // If MI def and/or use the same register multiple times, then there
+ // are multiple entries.
+ unsigned NumUses = MIHasUse;
+ while (i != e && RewriteMIs[i].MI == MI) {
+ assert(RewriteMIs[i].Index == index);
+ bool isUse = RewriteMIs[i].HasUse;
+ if (isUse) ++NumUses;
+ MIHasUse |= isUse;
+ MIHasDef |= RewriteMIs[i].HasDef;
+ ++i;
+ }
+ MachineBasicBlock *MBB = MI->getParent();
+
+ if (ImpUse && MI != ReMatDefMI) {
+ // Re-matting an instruction with virtual register use. Update the
+ // register interval's spill weight to HUGE_VALF to prevent it from
+ // being spilled.
+ LiveInterval &ImpLi = getInterval(ImpUse);
+ ImpLi.weight = HUGE_VALF;
+ }
- const LoopInfo &LI = getAnalysis<LoopInfo>();
- if (LI.begin() == LI.end()) {
- // If there are no loops in the function, join intervals in function order.
- for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
- I != E; ++I)
- joinIntervalsInMachineBB(I);
- } else {
- // Otherwise, join intervals in inner loops before other intervals.
- // Unfortunately we can't just iterate over loop hierarchy here because
- // there may be more MBB's than BB's. Collect MBB's for sorting.
- std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
- for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
- I != E; ++I)
- MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
-
- // Sort by loop depth.
- std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
-
- // Finally, join intervals in loop nest order.
- for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
- joinIntervalsInMachineBB(MBBs[i].second);
- }
-
- DEBUG(std::cerr << "*** Register mapping ***\n");
- DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
- if (r2rMap_[i]) {
- std::cerr << " reg " << i << " -> ";
- printRegName(r2rMap_[i]);
- std::cerr << "\n";
- });
-}
-
-/// Return true if the two specified registers belong to different register
-/// classes. The registers may be either phys or virt regs.
-bool LiveIntervals::differingRegisterClasses(unsigned RegA,
- unsigned RegB) const {
-
- // Get the register classes for the first reg.
- if (MRegisterInfo::isPhysicalRegister(RegA)) {
- assert(MRegisterInfo::isVirtualRegister(RegB) &&
- "Shouldn't consider two physregs!");
- return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
- }
-
- // Compare against the regclass for the second reg.
- const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
- if (MRegisterInfo::isVirtualRegister(RegB))
- return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
- else
- return !RegClass->contains(RegB);
-}
+ unsigned MBBId = MBB->getNumber();
+ unsigned ThisVReg = 0;
+ if (TrySplit) {
+ std::map<unsigned,unsigned>::const_iterator NVI = MBBVRegsMap.find(MBBId);
+ if (NVI != MBBVRegsMap.end()) {
+ ThisVReg = NVI->second;
+ // One common case:
+ // x = use
+ // ...
+ // ...
+ // def = ...
+ // = use
+ // It's better to start a new interval to avoid artifically
+ // extend the new interval.
+ if (MIHasDef && !MIHasUse) {
+ MBBVRegsMap.erase(MBB->getNumber());
+ ThisVReg = 0;
+ }
+ }
+ }
+
+ bool IsNew = ThisVReg == 0;
+ if (IsNew) {
+ // This ends the previous live interval. If all of its def / use
+ // can be folded, give it a low spill weight.
+ if (NewVReg && TrySplit && AllCanFold) {
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+ nI.weight /= 10.0F;
+ }
+ AllCanFold = true;
+ }
+ NewVReg = ThisVReg;
+
+ bool HasDef = false;
+ bool HasUse = false;
+ bool CanFold = rewriteInstructionForSpills(li, I->valno, TrySplit,
+ index, end, MI, ReMatOrigDefMI, ReMatDefMI,
+ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
+ CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
+ ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight);
+ if (!HasDef && !HasUse)
+ continue;
+
+ AllCanFold &= CanFold;
+
+ // Update weight of spill interval.
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+ if (!TrySplit) {
+ // The spill weight is now infinity as it cannot be spilled again.
+ nI.weight = HUGE_VALF;
+ continue;
+ }
+
+ // Keep track of the last def and first use in each MBB.
+ if (HasDef) {
+ if (MI != ReMatOrigDefMI || !CanDelete) {
+ bool HasKill = false;
+ if (!HasUse)
+ HasKill = anyKillInMBBAfterIdx(li, I->valno, MBB, getDefIndex(index));
+ else {
+ // If this is a two-address code, then this index starts a new VNInfo.
+ const VNInfo *VNI = li.findDefinedVNInfo(getDefIndex(index));
+ if (VNI)
+ HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index));
+ }
+ std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ SpillIdxes.find(MBBId);
+ if (!HasKill) {
+ if (SII == SpillIdxes.end()) {
+ std::vector<SRInfo> S;
+ S.push_back(SRInfo(index, NewVReg, true));
+ SpillIdxes.insert(std::make_pair(MBBId, S));
+ } else if (SII->second.back().vreg != NewVReg) {
+ SII->second.push_back(SRInfo(index, NewVReg, true));
+ } else if ((int)index > SII->second.back().index) {
+ // If there is an earlier def and this is a two-address
+ // instruction, then it's not possible to fold the store (which
+ // would also fold the load).
+ SRInfo &Info = SII->second.back();
+ Info.index = index;
+ Info.canFold = !HasUse;
+ }
+ SpillMBBs.set(MBBId);
+ } else if (SII != SpillIdxes.end() &&
+ SII->second.back().vreg == NewVReg &&
+ (int)index > SII->second.back().index) {
+ // There is an earlier def that's not killed (must be two-address).
+ // The spill is no longer needed.
+ SII->second.pop_back();
+ if (SII->second.empty()) {
+ SpillIdxes.erase(MBBId);
+ SpillMBBs.reset(MBBId);
+ }
+ }
+ }
+ }
+
+ if (HasUse) {
+ std::map<unsigned, std::vector<SRInfo> >::iterator SII =
+ SpillIdxes.find(MBBId);
+ if (SII != SpillIdxes.end() &&
+ SII->second.back().vreg == NewVReg &&
+ (int)index > SII->second.back().index)
+ // Use(s) following the last def, it's not safe to fold the spill.
+ SII->second.back().canFold = false;
+ std::map<unsigned, std::vector<SRInfo> >::iterator RII =
+ RestoreIdxes.find(MBBId);
+ if (RII != RestoreIdxes.end() && RII->second.back().vreg == NewVReg)
+ // If we are splitting live intervals, only fold if it's the first
+ // use and there isn't another use later in the MBB.
+ RII->second.back().canFold = false;
+ else if (IsNew) {
+ // Only need a reload if there isn't an earlier def / use.
+ if (RII == RestoreIdxes.end()) {
+ std::vector<SRInfo> Infos;
+ Infos.push_back(SRInfo(index, NewVReg, true));
+ RestoreIdxes.insert(std::make_pair(MBBId, Infos));
+ } else {
+ RII->second.push_back(SRInfo(index, NewVReg, true));
+ }
+ RestoreMBBs.set(MBBId);
+ }
+ }
-bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
- const LiveInterval *RHS) const {
- if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
- if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
- return false; // vreg-vreg merge has no aliases!
- std::swap(LHS, RHS);
+ // Update spill weight.
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+ nI.weight += getSpillWeight(HasDef, HasUse, loopDepth);
}
- assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
- MRegisterInfo::isVirtualRegister(RHS->reg) &&
- "first interval must describe a physical register");
+ if (NewVReg && TrySplit && AllCanFold) {
+ // If all of its def / use can be folded, give it a low spill weight.
+ LiveInterval &nI = getOrCreateInterval(NewVReg);
+ nI.weight /= 10.0F;
+ }
+}
- for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
- if (RHS->overlaps(getInterval(*AS)))
+bool LiveIntervals::alsoFoldARestore(int Id, int index, unsigned vr,
+ BitVector &RestoreMBBs,
+ std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ if (!RestoreMBBs[Id])
+ return false;
+ std::vector<SRInfo> &Restores = RestoreIdxes[Id];
+ for (unsigned i = 0, e = Restores.size(); i != e; ++i)
+ if (Restores[i].index == index &&
+ Restores[i].vreg == vr &&
+ Restores[i].canFold)
return true;
+ return false;
+}
+
+void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
+ BitVector &RestoreMBBs,
+ std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes) {
+ if (!RestoreMBBs[Id])
+ return;
+ std::vector<SRInfo> &Restores = RestoreIdxes[Id];
+ for (unsigned i = 0, e = Restores.size(); i != e; ++i)
+ if (Restores[i].index == index && Restores[i].vreg)
+ Restores[i].index = -1;
+}
+
+/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
+/// spilled and create empty intervals for their uses.
+void
+LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
+ const TargetRegisterClass* rc,
+ std::vector<LiveInterval*> &NewLIs) {
+ for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(li.reg),
+ re = mri_->reg_end(); ri != re; ) {
+ MachineOperand &O = ri.getOperand();
+ MachineInstr *MI = &*ri;
+ ++ri;
+ if (O.isDef()) {
+ assert(MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF &&
+ "Register def was not rewritten?");
+ RemoveMachineInstrFromMaps(MI);
+ vrm.RemoveMachineInstrFromMaps(MI);
+ MI->eraseFromParent();
+ } else {
+ // This must be an use of an implicit_def so it's not part of the live
+ // interval. Create a new empty live interval for it.
+ // FIXME: Can we simply erase some of the instructions? e.g. Stores?
+ unsigned NewVReg = mri_->createVirtualRegister(rc);
+ vrm.grow();
+ vrm.setIsImplicitlyDefined(NewVReg);
+ NewLIs.push_back(&getOrCreateInterval(NewVReg));
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.getReg() == li.reg)
+ MO.setReg(NewVReg);
+ }
+ }
+ }
+}
+
+
+std::vector<LiveInterval*> LiveIntervals::
+addIntervalsForSpills(const LiveInterval &li,
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
+ float &SSWeight) {
+ // Since this is called after the analysis is done we don't know if
+ // LiveVariables is available
+ lv_ = getAnalysisToUpdate<LiveVariables>();
+
+ assert(li.weight != HUGE_VALF &&
+ "attempt to spill already spilled interval!");
+
+ DOUT << "\t\t\t\tadding intervals for spills for interval: ";
+ li.print(DOUT, tri_);
+ DOUT << '\n';
+
+ // Spill slot weight.
+ SSWeight = 0.0f;
+
+ // Each bit specify whether it a spill is required in the MBB.
+ BitVector SpillMBBs(mf_->getNumBlockIDs());
+ std::map<unsigned, std::vector<SRInfo> > SpillIdxes;
+ BitVector RestoreMBBs(mf_->getNumBlockIDs());
+ std::map<unsigned, std::vector<SRInfo> > RestoreIdxes;
+ std::map<unsigned,unsigned> MBBVRegsMap;
+ std::vector<LiveInterval*> NewLIs;
+ const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
+
+ unsigned NumValNums = li.getNumValNums();
+ SmallVector<MachineInstr*, 4> ReMatDefs;
+ ReMatDefs.resize(NumValNums, NULL);
+ SmallVector<MachineInstr*, 4> ReMatOrigDefs;
+ ReMatOrigDefs.resize(NumValNums, NULL);
+ SmallVector<int, 4> ReMatIds;
+ ReMatIds.resize(NumValNums, VirtRegMap::MAX_STACK_SLOT);
+ BitVector ReMatDelete(NumValNums);
+ unsigned Slot = VirtRegMap::MAX_STACK_SLOT;
+
+ // Spilling a split live interval. It cannot be split any further. Also,
+ // it's also guaranteed to be a single val# / range interval.
+ if (vrm.getPreSplitReg(li.reg)) {
+ vrm.setIsSplitFromReg(li.reg, 0);
+ // Unset the split kill marker on the last use.
+ unsigned KillIdx = vrm.getKillPoint(li.reg);
+ if (KillIdx) {
+ MachineInstr *KillMI = getInstructionFromIndex(KillIdx);
+ assert(KillMI && "Last use disappeared?");
+ int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true);
+ assert(KillOp != -1 && "Last use disappeared?");
+ KillMI->getOperand(KillOp).setIsKill(false);
+ }
+ vrm.removeKillPoint(li.reg);
+ bool DefIsReMat = vrm.isReMaterialized(li.reg);
+ Slot = vrm.getStackSlot(li.reg);
+ assert(Slot != VirtRegMap::MAX_STACK_SLOT);
+ MachineInstr *ReMatDefMI = DefIsReMat ?
+ vrm.getReMaterializedMI(li.reg) : NULL;
+ int LdSlot = 0;
+ bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
+ bool isLoad = isLoadSS ||
+ (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
+ bool IsFirstRange = true;
+ for (LiveInterval::Ranges::const_iterator
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ // If this is a split live interval with multiple ranges, it means there
+ // are two-address instructions that re-defined the value. Only the
+ // first def can be rematerialized!
+ if (IsFirstRange) {
+ // Note ReMatOrigDefMI has already been deleted.
+ rewriteInstructionsForSpills(li, false, I, NULL, ReMatDefMI,
+ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
+ false, vrm, rc, ReMatIds, loopInfo,
+ SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
+ MBBVRegsMap, NewLIs, SSWeight);
+ } else {
+ rewriteInstructionsForSpills(li, false, I, NULL, 0,
+ Slot, 0, false, false, false,
+ false, vrm, rc, ReMatIds, loopInfo,
+ SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
+ MBBVRegsMap, NewLIs, SSWeight);
+ }
+ IsFirstRange = false;
+ }
+
+ SSWeight = 0.0f; // Already accounted for when split.
+ handleSpilledImpDefs(li, vrm, rc, NewLIs);
+ return NewLIs;
+ }
+
+ bool TrySplit = SplitAtBB && !intervalIsInOneMBB(li);
+ if (SplitLimit != -1 && (int)numSplits >= SplitLimit)
+ TrySplit = false;
+ if (TrySplit)
+ ++numSplits;
+ bool NeedStackSlot = false;
+ for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
+ i != e; ++i) {
+ const VNInfo *VNI = *i;
+ unsigned VN = VNI->id;
+ unsigned DefIdx = VNI->def;
+ if (DefIdx == ~1U)
+ continue; // Dead val#.
+ // Is the def for the val# rematerializable?
+ MachineInstr *ReMatDefMI = (DefIdx == ~0u)
+ ? 0 : getInstructionFromIndex(DefIdx);
+ bool dummy;
+ if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, dummy)) {
+ // Remember how to remat the def of this val#.
+ ReMatOrigDefs[VN] = ReMatDefMI;
+ // Original def may be modified so we have to make a copy here. vrm must
+ // delete these!
+ ReMatDefs[VN] = ReMatDefMI = ReMatDefMI->clone();
+
+ bool CanDelete = true;
+ if (VNI->hasPHIKill) {
+ // A kill is a phi node, not all of its uses can be rematerialized.
+ // It must not be deleted.
+ CanDelete = false;
+ // Need a stack slot if there is any live range where uses cannot be
+ // rematerialized.
+ NeedStackSlot = true;
+ }
+ if (CanDelete)
+ ReMatDelete.set(VN);
+ } else {
+ // Need a stack slot if there is any live range where uses cannot be
+ // rematerialized.
+ NeedStackSlot = true;
+ }
+ }
+
+ // One stack slot per live interval.
+ if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0)
+ Slot = vrm.assignVirt2StackSlot(li.reg);
+
+ // Create new intervals and rewrite defs and uses.
+ for (LiveInterval::Ranges::const_iterator
+ I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
+ MachineInstr *ReMatDefMI = ReMatDefs[I->valno->id];
+ MachineInstr *ReMatOrigDefMI = ReMatOrigDefs[I->valno->id];
+ bool DefIsReMat = ReMatDefMI != NULL;
+ bool CanDelete = ReMatDelete[I->valno->id];
+ int LdSlot = 0;
+ bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
+ bool isLoad = isLoadSS ||
+ (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
+ rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
+ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
+ CanDelete, vrm, rc, ReMatIds, loopInfo,
+ SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
+ MBBVRegsMap, NewLIs, SSWeight);
+ }
+
+ // Insert spills / restores if we are splitting.
+ if (!TrySplit) {
+ handleSpilledImpDefs(li, vrm, rc, NewLIs);
+ return NewLIs;
+ }
+
+ SmallPtrSet<LiveInterval*, 4> AddedKill;
+ SmallVector<unsigned, 2> Ops;
+ if (NeedStackSlot) {
+ int Id = SpillMBBs.find_first();
+ while (Id != -1) {
+ MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+ std::vector<SRInfo> &spills = SpillIdxes[Id];
+ for (unsigned i = 0, e = spills.size(); i != e; ++i) {
+ int index = spills[i].index;
+ unsigned VReg = spills[i].vreg;
+ LiveInterval &nI = getOrCreateInterval(VReg);
+ bool isReMat = vrm.isReMaterialized(VReg);
+ MachineInstr *MI = getInstructionFromIndex(index);
+ bool CanFold = false;
+ bool FoundUse = false;
+ Ops.clear();
+ if (spills[i].canFold) {
+ CanFold = true;
+ for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
+ MachineOperand &MO = MI->getOperand(j);
+ if (!MO.isRegister() || MO.getReg() != VReg)
+ continue;
+
+ Ops.push_back(j);
+ if (MO.isDef())
+ continue;
+ if (isReMat ||
+ (!FoundUse && !alsoFoldARestore(Id, index, VReg,
+ RestoreMBBs, RestoreIdxes))) {
+ // MI has two-address uses of the same register. If the use
+ // isn't the first and only use in the BB, then we can't fold
+ // it. FIXME: Move this to rewriteInstructionsForSpills.
+ CanFold = false;
+ break;
+ }
+ FoundUse = true;
+ }
+ }
+ // Fold the store into the def if possible.
+ bool Folded = false;
+ if (CanFold && !Ops.empty()) {
+ if (tryFoldMemoryOperand(MI, vrm, NULL, index, Ops, true, Slot,VReg)){
+ Folded = true;
+ if (FoundUse > 0) {
+ // Also folded uses, do not issue a load.
+ eraseRestoreInfo(Id, index, VReg, RestoreMBBs, RestoreIdxes);
+ nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
+ }
+ nI.removeRange(getDefIndex(index), getStoreIndex(index));
+ }
+ }
+
+ // Otherwise tell the spiller to issue a spill.
+ if (!Folded) {
+ LiveRange *LR = &nI.ranges[nI.ranges.size()-1];
+ bool isKill = LR->end == getStoreIndex(index);
+ if (!MI->registerDefIsDead(nI.reg))
+ // No need to spill a dead def.
+ vrm.addSpillPoint(VReg, isKill, MI);
+ if (isKill)
+ AddedKill.insert(&nI);
+ }
+
+ // Update spill slot weight.
+ if (!isReMat)
+ SSWeight += getSpillWeight(true, false, loopDepth);
+ }
+ Id = SpillMBBs.find_next(Id);
+ }
+ }
+ int Id = RestoreMBBs.find_first();
+ while (Id != -1) {
+ MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
+ unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+
+ std::vector<SRInfo> &restores = RestoreIdxes[Id];
+ for (unsigned i = 0, e = restores.size(); i != e; ++i) {
+ int index = restores[i].index;
+ if (index == -1)
+ continue;
+ unsigned VReg = restores[i].vreg;
+ LiveInterval &nI = getOrCreateInterval(VReg);
+ bool isReMat = vrm.isReMaterialized(VReg);
+ MachineInstr *MI = getInstructionFromIndex(index);
+ bool CanFold = false;
+ Ops.clear();
+ if (restores[i].canFold) {
+ CanFold = true;
+ for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
+ MachineOperand &MO = MI->getOperand(j);
+ if (!MO.isRegister() || MO.getReg() != VReg)
+ continue;
+
+ if (MO.isDef()) {
+ // If this restore were to be folded, it would have been folded
+ // already.
+ CanFold = false;
+ break;
+ }
+ Ops.push_back(j);
+ }
+ }
+
+ // Fold the load into the use if possible.
+ bool Folded = false;
+ if (CanFold && !Ops.empty()) {
+ if (!isReMat)
+ Folded = tryFoldMemoryOperand(MI, vrm, NULL,index,Ops,true,Slot,VReg);
+ else {
+ MachineInstr *ReMatDefMI = vrm.getReMaterializedMI(VReg);
+ int LdSlot = 0;
+ bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
+ // If the rematerializable def is a load, also try to fold it.
+ if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
+ Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
+ Ops, isLoadSS, LdSlot, VReg);
+ unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI);
+ if (ImpUse) {
+ // Re-matting an instruction with virtual register use. Add the
+ // register as an implicit use on the use MI and update the register
+ // interval's spill weight to HUGE_VALF to prevent it from being
+ // spilled.
+ LiveInterval &ImpLi = getInterval(ImpUse);
+ ImpLi.weight = HUGE_VALF;
+ MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
+ }
+ }
+ }
+ // If folding is not possible / failed, then tell the spiller to issue a
+ // load / rematerialization for us.
+ if (Folded)
+ nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
+ else
+ vrm.addRestorePoint(VReg, MI);
+
+ // Update spill slot weight.
+ if (!isReMat)
+ SSWeight += getSpillWeight(false, true, loopDepth);
+ }
+ Id = RestoreMBBs.find_next(Id);
+ }
+
+ // Finalize intervals: add kills, finalize spill weights, and filter out
+ // dead intervals.
+ std::vector<LiveInterval*> RetNewLIs;
+ for (unsigned i = 0, e = NewLIs.size(); i != e; ++i) {
+ LiveInterval *LI = NewLIs[i];
+ if (!LI->empty()) {
+ LI->weight /= LI->getSize();
+ if (!AddedKill.count(LI)) {
+ LiveRange *LR = &LI->ranges[LI->ranges.size()-1];
+ unsigned LastUseIdx = getBaseIndex(LR->end);
+ MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
+ int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false);
+ assert(UseIdx != -1);
+ if (LastUse->getOperand(UseIdx).isImplicit() ||
+ LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){
+ LastUse->getOperand(UseIdx).setIsKill();
+ vrm.addKillPoint(LI->reg, LastUseIdx);
+ }
+ }
+ RetNewLIs.push_back(LI);
+ }
+ }
+
+ handleSpilledImpDefs(li, vrm, rc, RetNewLIs);
+ return RetNewLIs;
+}
+
+/// hasAllocatableSuperReg - Return true if the specified physical register has
+/// any super register that's allocatable.
+bool LiveIntervals::hasAllocatableSuperReg(unsigned Reg) const {
+ for (const unsigned* AS = tri_->getSuperRegisters(Reg); *AS; ++AS)
+ if (allocatableRegs_[*AS] && hasInterval(*AS))
+ return true;
return false;
}
-LiveInterval LiveIntervals::createInterval(unsigned reg) {
- float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
- (float)HUGE_VAL :0.0F;
- return LiveInterval(reg, Weight);
+/// getRepresentativeReg - Find the largest super register of the specified
+/// physical register.
+unsigned LiveIntervals::getRepresentativeReg(unsigned Reg) const {
+ // Find the largest super-register that is allocatable.
+ unsigned BestReg = Reg;
+ for (const unsigned* AS = tri_->getSuperRegisters(Reg); *AS; ++AS) {
+ unsigned SuperReg = *AS;
+ if (!hasAllocatableSuperReg(SuperReg) && hasInterval(SuperReg)) {
+ BestReg = SuperReg;
+ break;
+ }
+ }
+ return BestReg;
+}
+
+/// getNumConflictsWithPhysReg - Return the number of uses and defs of the
+/// specified interval that conflicts with the specified physical register.
+unsigned LiveIntervals::getNumConflictsWithPhysReg(const LiveInterval &li,
+ unsigned PhysReg) const {
+ unsigned NumConflicts = 0;
+ const LiveInterval &pli = getInterval(getRepresentativeReg(PhysReg));
+ for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
+ E = mri_->reg_end(); I != E; ++I) {
+ MachineOperand &O = I.getOperand();
+ MachineInstr *MI = O.getParent();
+ unsigned Index = getInstructionIndex(MI);
+ if (pli.liveAt(Index))
+ ++NumConflicts;
+ }
+ return NumConflicts;
+}
+
+/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
+/// around all defs and uses of the specified interval.
+void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li,
+ unsigned PhysReg, VirtRegMap &vrm) {
+ unsigned SpillReg = getRepresentativeReg(PhysReg);
+
+ for (const unsigned *AS = tri_->getAliasSet(PhysReg); *AS; ++AS)
+ // If there are registers which alias PhysReg, but which are not a
+ // sub-register of the chosen representative super register. Assert
+ // since we can't handle it yet.
+ assert(*AS == SpillReg || !allocatableRegs_[*AS] ||
+ tri_->isSuperRegister(*AS, SpillReg));
+
+ LiveInterval &pli = getInterval(SpillReg);
+ SmallPtrSet<MachineInstr*, 8> SeenMIs;
+ for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg),
+ E = mri_->reg_end(); I != E; ++I) {
+ MachineOperand &O = I.getOperand();
+ MachineInstr *MI = O.getParent();
+ if (SeenMIs.count(MI))
+ continue;
+ SeenMIs.insert(MI);
+ unsigned Index = getInstructionIndex(MI);
+ if (pli.liveAt(Index)) {
+ vrm.addEmergencySpill(SpillReg, MI);
+ pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
+ for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
+ if (!hasInterval(*AS))
+ continue;
+ LiveInterval &spli = getInterval(*AS);
+ if (spli.liveAt(Index))
+ spli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1);
+ }
+ }
+ }
+}
+
+LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
+ MachineInstr* startInst) {
+ LiveInterval& Interval = getOrCreateInterval(reg);
+ VNInfo* VN = Interval.getNextValue(
+ getInstructionIndex(startInst) + InstrSlots::DEF,
+ startInst, getVNInfoAllocator());
+ VN->hasPHIKill = true;
+ VN->kills.push_back(getMBBEndIdx(startInst->getParent()));
+ LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF,
+ getMBBEndIdx(startInst->getParent()) + 1, VN);
+ Interval.addRange(LR);
+
+ return LR;
}