// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
+ if (mi->isRegTiedToUseOperand(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
goto exit;
- } else if (mi->modifiesRegister(interval.reg, tri_)) {
- // Another instruction redefines the register before it is ever read.
- // Then the register is essentially dead at the instruction that defines
- // it. Hence its interval is:
- // [defSlot(def), defSlot(def)+1)
- DOUT << " dead";
- end = start + 1;
- goto exit;
+ } else {
+ int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_);
+ if (DefIdx != -1) {
+ if (mi->isRegTiedToUseOperand(DefIdx)) {
+ // Two-address instruction.
+ end = getDefIndex(baseIndex);
+ if (mi->getOperand(DefIdx).isEarlyClobber())
+ end = getUseIndex(baseIndex);
+ } else {
+ // Another instruction redefines the register before it is ever read.
+ // Then the register is essentially dead at the instruction that defines
+ // it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ DOUT << " dead";
+ end = start + 1;
+ }
+ goto exit;
+ }
}
baseIndex += InstrSlots::NUM;
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
- // and never used.
- assert(!CopyMI && "physreg was not killed in defining block!");
+ // and never used. Another possible case is the implicit use of the
+ // physical register has been deleted by two-address pass.
end = start + 1;
exit:
MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = MI;
- handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()), CopyMI);
// Def of a register also defines its sub-registers.
for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS)
// If MI also modifies the sub-register explicitly, avoid processing it
// more than once. Do not pass in TRI here so it checks for exact match.
if (!MI->modifiesRegister(*AS))
- handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(*AS), 0);
}
}
const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
- MachineBasicBlock *MBB = MI->getParent();
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+ std::vector<LiveInterval*> &NewLIs) {
bool CanFold = false;
RestartInstruction:
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
// the INSERT_SUBREG and both target registers that would overlap.
HasUse = false;
- // Update stack slot spill weight if we are splitting.
- float Weight = getSpillWeight(HasDef, HasUse, loopDepth);
- if (!TrySplit)
- SSWeight += Weight;
-
// Create a new virtual register for the spill interval.
// Create the new register now so we can map the fold instruction
// to the new register so when it is unfolded we get the correct
HasUse = false;
HasDef = false;
CanFold = false;
- if (isRemoved(MI)) {
- SSWeight -= Weight;
+ if (isNotInMIMap(MI))
break;
- }
goto RestartInstruction;
}
} else {
if (DefIsReMat && ImpUse)
MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
- // create a new register interval for this spill / remat.
+ // Create a new register interval for this spill / remat.
LiveInterval &nI = getOrCreateInterval(NewVReg);
if (CreatedNewVReg) {
NewLIs.push_back(&nI);
BitVector &RestoreMBBs,
DenseMap<unsigned, std::vector<SRInfo> > &RestoreIdxes,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
+ std::vector<LiveInterval*> &NewLIs) {
bool AllCanFold = true;
unsigned NewVReg = 0;
unsigned start = getBaseIndex(I->start);
index, end, MI, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
- ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight);
+ ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs);
if (!HasDef && !HasUse)
continue;
}
}
-namespace {
- struct LISorter {
- bool operator()(LiveInterval* A, LiveInterval* B) {
- return A->beginNumber() < B->beginNumber();
- }
- };
-}
-
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpillsFast(const LiveInterval &li,
const MachineLoopInfo *loopInfo,
- VirtRegMap &vrm, float& SSWeight) {
+ VirtRegMap &vrm) {
unsigned slot = vrm.assignVirt2StackSlot(li.reg);
std::vector<LiveInterval*> added;
const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
- SSWeight = 0.0f;
-
MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg);
while (RI != mri_->reg_end()) {
MachineInstr* MI = &*RI;
DOUT << "\t\t\t\tadded new interval: ";
DEBUG(nI.dump());
DOUT << '\n';
-
- unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
- if (HasUse) {
- if (HasDef)
- SSWeight += getSpillWeight(true, true, loopDepth);
- else
- SSWeight += getSpillWeight(false, true, loopDepth);
- } else
- SSWeight += getSpillWeight(true, false, loopDepth);
}
RI = mri_->reg_begin(li.reg);
}
- // Clients expect the new intervals to be returned in sorted order.
- std::sort(added.begin(), added.end(), LISorter());
-
return added;
}
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li,
SmallVectorImpl<LiveInterval*> &SpillIs,
- const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
- float &SSWeight) {
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm) {
if (EnableFastSpilling)
- return addIntervalsForSpillsFast(li, loopInfo, vrm, SSWeight);
+ return addIntervalsForSpillsFast(li, loopInfo, vrm);
assert(li.weight != HUGE_VALF &&
"attempt to spill already spilled interval!");
li.print(DOUT, tri_);
DOUT << '\n';
- // Spill slot weight.
- SSWeight = 0.0f;
-
// Each bit specify whether a spill is required in the MBB.
BitVector SpillMBBs(mf_->getNumBlockIDs());
DenseMap<unsigned, std::vector<SRInfo> > SpillIdxes;
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
} else {
rewriteInstructionsForSpills(li, false, I, NULL, 0,
Slot, 0, false, false, false,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
}
IsFirstRange = false;
}
- SSWeight = 0.0f; // Already accounted for when split.
handleSpilledImpDefs(li, vrm, rc, NewLIs);
return NewLIs;
}
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
}
// Insert spills / restores if we are splitting.
if (NeedStackSlot) {
int Id = SpillMBBs.find_first();
while (Id != -1) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
std::vector<SRInfo> &spills = SpillIdxes[Id];
for (unsigned i = 0, e = spills.size(); i != e; ++i) {
int index = spills[i].index;
if (isKill)
AddedKill.insert(&nI);
}
-
- // Update spill slot weight.
- if (!isReMat)
- SSWeight += getSpillWeight(true, false, loopDepth);
}
Id = SpillMBBs.find_next(Id);
}
int Id = RestoreMBBs.find_first();
while (Id != -1) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
-
std::vector<SRInfo> &restores = RestoreIdxes[Id];
for (unsigned i = 0, e = restores.size(); i != e; ++i) {
int index = restores[i].index;
nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
else
vrm.addRestorePoint(VReg, MI);
-
- // Update spill slot weight.
- if (!isReMat)
- SSWeight += getSpillWeight(false, true, loopDepth);
}
Id = RestoreMBBs.find_next(Id);
}
// If there are registers which alias PhysReg, but which are not a
// sub-register of the chosen representative super register. Assert
// since we can't handle it yet.
- assert(*AS == SpillReg || !allocatableRegs_[*AS] ||
+ assert(*AS == SpillReg || !allocatableRegs_[*AS] || !hasInterval(*AS) ||
tri_->isSuperRegister(*AS, SpillReg));
bool Cut = false;
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