cl::init(true), cl::Hidden);
static cl::opt<int> SplitLimit("split-limit",
cl::init(-1), cl::Hidden);
-static cl::opt<bool> EmptyBBIndex("empty-bb-index",
- cl::init(false), cl::Hidden);
STATISTIC(numIntervals, "Number of original intervals");
STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
// Release VNInfo memroy regions after all VNInfo objects are dtor'd.
VNInfoAllocator.Reset();
for (unsigned i = 0, e = ClonedMIs.size(); i != e; ++i)
- delete ClonedMIs[i];
+ mf_->DeleteMachineInstr(ClonedMIs[i]);
}
void LiveIntervals::computeNumbering() {
i2miMap_.push_back(I);
MIIndex += InstrSlots::NUM;
}
-
- // Set the MBB2IdxMap entry for this MBB.
- if (!EmptyBBIndex) {
- MBB2IdxMap[MBB->getNumber()] = (StartIdx == MIIndex)
- ? std::make_pair(StartIdx, StartIdx) // Empty MBB
- : std::make_pair(StartIdx, MIIndex - 1);
- Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
- } else {
- if (StartIdx == MIIndex) {
- // Empty MBB
- MIIndex += InstrSlots::NUM;
- i2miMap_.push_back(0);
- }
-
- MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
- Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
+
+ if (StartIdx == MIIndex) {
+ // Empty MBB
+ MIIndex += InstrSlots::NUM;
+ i2miMap_.push_back(0);
}
+ // Set the MBB2IdxMap entry for this MBB.
+ MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
+ Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
}
std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
- unsigned MIIdx,
+ unsigned MIIdx, MachineOperand& MO,
LiveInterval &interval) {
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
// live interval.
for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
if (vi.AliveBlocks[i]) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
- if (!MBB->empty()) {
- LiveRange LR(getMBBStartIdx(i),
- getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
- ValNo);
- interval.addRange(LR);
- DOUT << " +" << LR;
- }
+ LiveRange LR(getMBBStartIdx(i),
+ getMBBEndIdx(i)+1, // MBB ends at -1.
+ ValNo);
+ interval.addRange(LR);
+ DOUT << " +" << LR;
}
}
// If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot.
- if (mi->registerDefIsDead(interval.reg, tri_))
+ if (MO.isDead())
interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo));
DOUT << " RESULT: ";
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
unsigned MIIdx,
+ MachineOperand& MO,
LiveInterval &interval,
MachineInstr *CopyMI) {
// A physical register cannot be live across basic block, so its
// If it is not used after definition, it is considered dead at
// the instruction defining it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
- if (mi->registerDefIsDead(interval.reg, tri_)) {
+ if (MO.isDead()) {
DOUT << " dead";
end = getDefIndex(start) + 1;
goto exit;
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
unsigned MIIdx,
- unsigned reg) {
- if (TargetRegisterInfo::isVirtualRegister(reg))
- handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
- else if (allocatableRegs_[reg]) {
+ MachineOperand& MO) {
+ if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ handleVirtualRegisterDef(MBB, MI, MIIdx, MO,
+ getOrCreateInterval(MO.getReg()));
+ else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
tii_->isMoveInstr(*MI, SrcReg, DstReg))
CopyMI = MI;
- handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI);
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ getOrCreateInterval(MO.getReg()), CopyMI);
// Def of a register also defines its sub-registers.
- for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
+ for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS)
// If MI also modifies the sub-register explicitly, avoid processing it
// more than once. Do not pass in TRI here so it checks for exact match.
if (!MI->modifiesRegister(*AS))
- handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ getOrCreateInterval(*AS), 0);
}
}
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
if (MO.isRegister() && MO.getReg() && MO.isDef())
- handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
+ handleRegisterDef(MBB, MI, MIIndex, MO);
}
MIIndex += InstrSlots::NUM;
}
- if (EmptyBBIndex) {
- if (MBB->begin() == miEnd) MIIndex += InstrSlots::NUM; // Empty MBB
- }
+ if (MBB->begin() == miEnd) MIIndex += InstrSlots::NUM; // Empty MBB
}
}
// Attempt to fold the memory reference into the instruction. If
// we can do this, we don't need to insert spill code.
- if (lv_)
- lv_->instructionChanged(MI, fmi);
- else
- fmi->copyKillDeadInfo(MI, tri_);
MachineBasicBlock &MBB = *MI->getParent();
if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
addIntervalsForSpills(const LiveInterval &li,
const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
float &SSWeight) {
- // Since this is called after the analysis is done we don't know if
- // LiveVariables is available
- lv_ = getAnalysisToUpdate<LiveVariables>();
-
assert(li.weight != HUGE_VALF &&
"attempt to spill already spilled interval!");
ReMatOrigDefs[VN] = ReMatDefMI;
// Original def may be modified so we have to make a copy here. vrm must
// delete these!
- ReMatDefs[VN] = ReMatDefMI = ReMatDefMI->clone();
+ ReMatDefs[VN] = ReMatDefMI = mf_->CloneMachineInstr(ReMatDefMI);
bool CanDelete = true;
if (VNI->hasPHIKill) {
projects / oota-llvm.git / blobdiff