#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
+#include <limits>
#include <cmath>
using namespace llvm;
static RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
AU.addRequired<AliasAnalysis>();
AU.addPreserved<AliasAnalysis>();
AU.addPreserved<LiveVariables>();
mi2iMap_.clear();
i2miMap_.clear();
r2iMap_.clear();
+ terminatorGaps.clear();
+
// Release VNInfo memroy regions after all VNInfo objects are dtor'd.
VNInfoAllocator.Reset();
while (!ClonedMIs.empty()) {
}
}
+static bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg,
+ const TargetInstrInfo *tii_) {
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ Reg == SrcReg)
+ return true;
+
+ if ((MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
+ MI->getOperand(2).getReg() == Reg)
+ return true;
+ if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
+ MI->getOperand(1).getReg() == Reg)
+ return true;
+ return false;
+}
+
+/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
+/// there is one implicit_def for each use. Add isUndef marker to
+/// implicit_def defs and their uses.
+void LiveIntervals::processImplicitDefs() {
+ SmallSet<unsigned, 8> ImpDefRegs;
+ SmallVector<MachineInstr*, 8> ImpDefMIs;
+ MachineBasicBlock *Entry = mf_->begin();
+ SmallPtrSet<MachineBasicBlock*,16> Visited;
+ for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
+ DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
+ DFI != E; ++DFI) {
+ MachineBasicBlock *MBB = *DFI;
+ for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
+ I != E; ) {
+ MachineInstr *MI = &*I;
+ ++I;
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ unsigned Reg = MI->getOperand(0).getReg();
+ ImpDefRegs.insert(Reg);
+ ImpDefMIs.push_back(MI);
+ continue;
+ }
+
+ bool ChangedToImpDef = false;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isUse() || MO.isUndef())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ if (!ImpDefRegs.count(Reg))
+ continue;
+ // Use is a copy, just turn it into an implicit_def.
+ if (CanTurnIntoImplicitDef(MI, Reg, tii_)) {
+ bool isKill = MO.isKill();
+ MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
+ for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
+ MI->RemoveOperand(j);
+ if (isKill)
+ ImpDefRegs.erase(Reg);
+ ChangedToImpDef = true;
+ break;
+ }
+
+ MO.setIsUndef();
+ if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
+ // Make sure other uses of
+ for (unsigned j = i+1; j != e; ++j) {
+ MachineOperand &MOJ = MI->getOperand(j);
+ if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
+ MOJ.setIsUndef();
+ }
+ ImpDefRegs.erase(Reg);
+ }
+ }
+
+ if (ChangedToImpDef) {
+ // Backtrack to process this new implicit_def.
+ --I;
+ } else {
+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
+ MachineOperand& MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isDef())
+ continue;
+ ImpDefRegs.erase(MO.getReg());
+ }
+ }
+ }
+
+ // Any outstanding liveout implicit_def's?
+ for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
+ MachineInstr *MI = ImpDefMIs[i];
+ unsigned Reg = MI->getOperand(0).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
+ !ImpDefRegs.count(Reg)) {
+ // Delete all "local" implicit_def's. That include those which define
+ // physical registers since they cannot be liveout.
+ MI->eraseFromParent();
+ continue;
+ }
+
+ // If there are multiple defs of the same register and at least one
+ // is not an implicit_def, do not insert implicit_def's before the
+ // uses.
+ bool Skip = false;
+ for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
+ DE = mri_->def_end(); DI != DE; ++DI) {
+ if (DI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
+ Skip = true;
+ break;
+ }
+ }
+ if (Skip)
+ continue;
+
+ // The only implicit_def which we want to keep are those that are live
+ // out of its block.
+ MI->eraseFromParent();
+
+ for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
+ UE = mri_->use_end(); UI != UE; ) {
+ MachineOperand &RMO = UI.getOperand();
+ MachineInstr *RMI = &*UI;
+ ++UI;
+ MachineBasicBlock *RMBB = RMI->getParent();
+ if (RMBB == MBB)
+ continue;
+
+ // Turn a copy use into an implicit_def.
+ unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
+ if (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ Reg == SrcReg) {
+ RMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
+ for (int j = RMI->getNumOperands() - 1, ee = 0; j > ee; --j)
+ RMI->RemoveOperand(j);
+ continue;
+ }
+
+ const TargetRegisterClass* RC = mri_->getRegClass(Reg);
+ unsigned NewVReg = mri_->createVirtualRegister(RC);
+ RMO.setReg(NewVReg);
+ RMO.setIsUndef();
+ RMO.setIsKill();
+ }
+ }
+ ImpDefRegs.clear();
+ ImpDefMIs.clear();
+ }
+}
+
void LiveIntervals::computeNumbering() {
Index2MiMap OldI2MI = i2miMap_;
std::vector<IdxMBBPair> OldI2MBB = Idx2MBBMap;
MBB2IdxMap.clear();
mi2iMap_.clear();
i2miMap_.clear();
+ terminatorGaps.clear();
FunctionSize = 0;
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
+
+ if (I == MBB->getFirstTerminator()) {
+ // Leave a gap for before terminators, this is where we will point
+ // PHI kills.
+ bool inserted =
+ terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
+ assert(inserted &&
+ "Multiple 'first' terminators encountered during numbering.");
+ inserted = inserted; // Avoid compiler warning if assertions turned off.
+ i2miMap_.push_back(0);
+
+ MIIndex += InstrSlots::NUM;
+ }
+
bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
inserted = true;
while (Slots--)
i2miMap_.push_back(0);
}
+
+ if (MBB->getFirstTerminator() == MBB->end()) {
+ // Leave a gap for before terminators, this is where we will point
+ // PHI kills.
+ bool inserted =
+ terminatorGaps.insert(std::make_pair(&*MBB, MIIndex)).second;
+ assert(inserted &&
+ "Multiple 'first' terminators encountered during numbering.");
+ inserted = inserted; // Avoid compiler warning if assertions turned off.
+ i2miMap_.push_back(0);
+
+ MIIndex += InstrSlots::NUM;
+ }
// Set the MBB2IdxMap entry for this MBB.
MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
Idx2MBBMap.push_back(std::make_pair(StartIdx, MBB));
}
+
std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
if (!OldI2MI.empty())
// Remap the VNInfo def index, which works the same as the
// start indices above. VN's with special sentinel defs
// don't need to be remapped.
- if (vni->def != ~0U && vni->def != ~1U) {
+ if (vni->isDefAccurate() && !vni->isUnused()) {
unsigned index = vni->def / InstrSlots::NUM;
unsigned offset = vni->def % InstrSlots::NUM;
if (offset == InstrSlots::LOAD) {
// Remap the VNInfo kill indices, which works the same as
// the end indices above.
for (size_t i = 0; i < vni->kills.size(); ++i) {
- // PHI kills don't need to be remapped.
- if (!vni->kills[i]) continue;
-
- unsigned index = (vni->kills[i]-1) / InstrSlots::NUM;
- unsigned offset = vni->kills[i] % InstrSlots::NUM;
+ unsigned killIdx = vni->kills[i].killIdx;
+
+ unsigned index = (killIdx - 1) / InstrSlots::NUM;
+ unsigned offset = killIdx % InstrSlots::NUM;
+
if (offset == InstrSlots::LOAD) {
- std::vector<IdxMBBPair>::const_iterator I =
+ assert("Value killed at a load slot.");
+ /*std::vector<IdxMBBPair>::const_iterator I =
std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), vni->kills[i]);
--I;
- vni->kills[i] = getMBBEndIdx(I->second);
+ vni->kills[i] = getMBBEndIdx(I->second);*/
} else {
+ if (vni->kills[i].isPHIKill) {
+ std::vector<IdxMBBPair>::const_iterator I =
+ std::lower_bound(OldI2MBB.begin(), OldI2MBB.end(), index);
+ --I;
+ vni->kills[i].killIdx = terminatorGaps[I->second];
+ } else {
+ assert(OldI2MI[index] != 0 &&
+ "Kill refers to instruction not present in index maps.");
+ vni->kills[i].killIdx = mi2iMap_[OldI2MI[index]] + offset;
+ }
+
+ /*
unsigned idx = index;
while (index < OldI2MI.size() && !OldI2MI[index]) ++index;
(idx == index ? offset : 0);
else
vni->kills[i] = InstrSlots::NUM * i2miMap_.size();
+ */
}
}
}
}
}
+void LiveIntervals::scaleNumbering(int factor) {
+ // Need to
+ // * scale MBB begin and end points
+ // * scale all ranges.
+ // * Update VNI structures.
+ // * Scale instruction numberings
+
+ // Scale the MBB indices.
+ Idx2MBBMap.clear();
+ for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end();
+ MBB != MBBE; ++MBB) {
+ std::pair<unsigned, unsigned> &mbbIndices = MBB2IdxMap[MBB->getNumber()];
+ mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor);
+ mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor);
+ Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB));
+ }
+ std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
+
+ // Scale terminator gaps.
+ for (DenseMap<MachineBasicBlock*, unsigned>::iterator
+ TGI = terminatorGaps.begin(), TGE = terminatorGaps.end();
+ TGI != TGE; ++TGI) {
+ terminatorGaps[TGI->first] = InstrSlots::scale(TGI->second, factor);
+ }
+
+ // Scale the intervals.
+ for (iterator LI = begin(), LE = end(); LI != LE; ++LI) {
+ LI->second->scaleNumbering(factor);
+ }
+
+ // Scale MachineInstrs.
+ Mi2IndexMap oldmi2iMap = mi2iMap_;
+ unsigned highestSlot = 0;
+ for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end();
+ MI != ME; ++MI) {
+ unsigned newSlot = InstrSlots::scale(MI->second, factor);
+ mi2iMap_[MI->first] = newSlot;
+ highestSlot = std::max(highestSlot, newSlot);
+ }
+
+ i2miMap_.clear();
+ i2miMap_.resize(highestSlot + 1);
+ for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end();
+ MI != ME; ++MI) {
+ i2miMap_[MI->second] = const_cast<MachineInstr *>(MI->first);
+ }
+
+}
+
+
/// runOnMachineFunction - Register allocate the whole function
///
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
lv_ = &getAnalysis<LiveVariables>();
allocatableRegs_ = tri_->getAllocatableSet(fn);
+ processImplicitDefs();
computeNumbering();
computeIntervals();
O << "********** MACHINEINSTRS **********\n";
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
- O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
+ O << ((Value*)mbbi->getBasicBlock())->getNameStr() << ":\n";
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
O << getInstructionIndex(mii) << '\t' << *mii;
void LiveIntervals::printRegName(unsigned reg) const {
if (TargetRegisterInfo::isPhysicalRegister(reg))
- cerr << tri_->getName(reg);
+ errs() << tri_->getName(reg);
else
- cerr << "%reg" << reg;
+ errs() << "%reg" << reg;
}
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
unsigned MOIdx,
LiveInterval &interval) {
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
- LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
-
- if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
- DOUT << "is a implicit_def\n";
- return;
- }
// Virtual registers may be defined multiple times (due to phi
// elimination and 2-addr elimination). Much of what we do only has to be
// done once for the vreg. We use an empty interval to detect the first
// time we see a vreg.
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (interval.empty()) {
// Get the Idx of the defining instructions.
unsigned defIndex = getDefIndex(MIIdx);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = mi;
// Earlyclobbers move back one.
- ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
+ ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
assert(ValNo->id == 0 && "First value in interval is not 0?");
// If the kill happens after the definition, we have an intra-block
// live range.
if (killIdx > defIndex) {
- assert(vi.AliveBlocks.none() &&
+ assert(vi.AliveBlocks.empty() &&
"Shouldn't be alive across any blocks!");
LiveRange LR(defIndex, killIdx, ValNo);
interval.addRange(LR);
DOUT << " +" << LR << "\n";
- interval.addKill(ValNo, killIdx);
+ interval.addKill(ValNo, killIdx, false);
return;
}
}
// Iterate over all of the blocks that the variable is completely
// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
// live interval.
- for (int i = vi.AliveBlocks.find_first(); i != -1;
- i = vi.AliveBlocks.find_next(i)) {
- LiveRange LR(getMBBStartIdx(i),
- getMBBEndIdx(i)+1, // MBB ends at -1.
+ for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
+ E = vi.AliveBlocks.end(); I != E; ++I) {
+ LiveRange LR(getMBBStartIdx(*I),
+ getMBBEndIdx(*I)+1, // MBB ends at -1.
ValNo);
interval.addRange(LR);
DOUT << " +" << LR;
LiveRange LR(getMBBStartIdx(Kill->getParent()),
killIdx, ValNo);
interval.addRange(LR);
- interval.addKill(ValNo, killIdx);
+ interval.addKill(ValNo, killIdx, false);
DOUT << " +" << LR;
}
// must be due to phi elimination or two addr elimination. If this is
// the result of two address elimination, then the vreg is one of the
// def-and-use register operand.
- if (mi->isRegReDefinedByTwoAddr(MOIdx)) {
+ if (mi->isRegTiedToUseOperand(MOIdx)) {
// If this is a two-address definition, then we have already processed
// the live range. The only problem is that we didn't realize there
// are actually two values in the live interval. Because of this we
// The new value number (#1) is defined by the instruction we claimed
// defined value #0.
- VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->copy,
+ VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->getCopy(),
+ false, // update at *
VNInfoAllocator);
-
+ ValNo->setFlags(OldValNo->getFlags()); // * <- updating here
+
// Value#0 is now defined by the 2-addr instruction.
OldValNo->def = RedefIndex;
- OldValNo->copy = 0;
+ OldValNo->setCopy(0);
if (MO.isEarlyClobber())
- OldValNo->redefByEC = true;
+ OldValNo->setHasRedefByEC(true);
// Add the new live interval which replaces the range for the input copy.
LiveRange LR(DefIndex, RedefIndex, ValNo);
DOUT << " replace range with " << LR;
interval.addRange(LR);
- interval.addKill(ValNo, RedefIndex);
+ interval.addKill(ValNo, RedefIndex, false);
// If this redefinition is dead, we need to add a dummy unit live
// range covering the def slot.
unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
DOUT << " Removing [" << Start << "," << End << "] from: ";
interval.print(DOUT, tri_); DOUT << "\n";
- interval.removeRange(Start, End);
- VNI->hasPHIKill = true;
+ interval.removeRange(Start, End);
+ assert(interval.ranges.size() == 1 &&
+ "newly discovered PHI interval has >1 ranges.");
+ MachineBasicBlock *killMBB = getMBBFromIndex(interval.endNumber());
+ interval.addKill(VNI, terminatorGaps[killMBB], true);
+ VNI->setHasPHIKill(true);
DOUT << " RESULT: "; interval.print(DOUT, tri_);
// Replace the interval with one of a NEW value number. Note that this
// value number isn't actually defined by an instruction, weird huh? :)
- LiveRange LR(Start, End, interval.getNextValue(~0, 0, VNInfoAllocator));
+ LiveRange LR(Start, End,
+ interval.getNextValue(mbb->getNumber(), 0, false, VNInfoAllocator));
+ LR.valno->setIsPHIDef(true);
DOUT << " replace range with " << LR;
interval.addRange(LR);
- interval.addKill(LR.valno, End);
+ interval.addKill(LR.valno, End, false);
DOUT << " RESULT: "; interval.print(DOUT, tri_);
}
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = mi;
- ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
+ ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
unsigned killIndex = getMBBEndIdx(mbb) + 1;
LiveRange LR(defIndex, killIndex, ValNo);
interval.addRange(LR);
- interval.addKill(ValNo, killIndex);
- ValNo->hasPHIKill = true;
+ interval.addKill(ValNo, terminatorGaps[mbb], true);
+ ValNo->setHasPHIKill(true);
DOUT << " +" << LR;
}
}
DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
goto exit;
- } else if (mi->modifiesRegister(interval.reg, tri_)) {
- // Another instruction redefines the register before it is ever read.
- // Then the register is essentially dead at the instruction that defines
- // it. Hence its interval is:
- // [defSlot(def), defSlot(def)+1)
- DOUT << " dead";
- end = start + 1;
- goto exit;
+ } else {
+ int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_);
+ if (DefIdx != -1) {
+ if (mi->isRegTiedToUseOperand(DefIdx)) {
+ // Two-address instruction.
+ end = getDefIndex(baseIndex);
+ if (mi->getOperand(DefIdx).isEarlyClobber())
+ end = getUseIndex(baseIndex);
+ } else {
+ // Another instruction redefines the register before it is ever read.
+ // Then the register is essentially dead at the instruction that defines
+ // it. Hence its interval is:
+ // [defSlot(def), defSlot(def)+1)
+ DOUT << " dead";
+ end = start + 1;
+ }
+ goto exit;
+ }
}
baseIndex += InstrSlots::NUM;
// The only case we should have a dead physreg here without a killing or
// instruction where we know it's dead is if it is live-in to the function
- // and never used.
- assert(!CopyMI && "physreg was not killed in defining block!");
+ // and never used. Another possible case is the implicit use of the
+ // physical register has been deleted by two-address pass.
end = start + 1;
exit:
LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
bool Extend = OldLR != interval.end();
VNInfo *ValNo = Extend
- ? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
+ ? OldLR->valno : interval.getNextValue(start, CopyMI, true, VNInfoAllocator);
if (MO.isEarlyClobber() && Extend)
- ValNo->redefByEC = true;
+ ValNo->setHasRedefByEC(true);
LiveRange LR(start, end, ValNo);
interval.addRange(LR);
- interval.addKill(LR.valno, end);
+ interval.addKill(LR.valno, end, false);
DOUT << " +" << LR << '\n';
}
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = MI;
- handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()), CopyMI);
// Def of a register also defines its sub-registers.
for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS)
// If MI also modifies the sub-register explicitly, avoid processing it
// more than once. Do not pass in TRI here so it checks for exact match.
if (!MI->modifiesRegister(*AS))
- handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
+ handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(*AS), 0);
}
}
DOUT << " killed";
end = getUseIndex(baseIndex) + 1;
SeenDefUse = true;
- goto exit;
+ break;
} else if (mi->modifiesRegister(interval.reg, tri_)) {
// Another instruction redefines the register before it is ever read.
// Then the register is essentially dead at the instruction that defines
DOUT << " dead";
end = getDefIndex(start) + 1;
SeenDefUse = true;
- goto exit;
+ break;
}
baseIndex += InstrSlots::NUM;
}
}
-exit:
// Live-in register might not be used at all.
if (!SeenDefUse) {
if (isAlias) {
}
}
- LiveRange LR(start, end, interval.getNextValue(~0U, 0, VNInfoAllocator));
+ VNInfo *vni =
+ interval.getNextValue(MBB->getNumber(), 0, false, VNInfoAllocator);
+ vni->setIsPHIDef(true);
+ LiveRange LR(start, end, vni);
+
interval.addRange(LR);
- interval.addKill(LR.valno, end);
+ interval.addKill(LR.valno, end, false);
DOUT << " +" << LR << '\n';
}
/// which a variable is live
void LiveIntervals::computeIntervals() {
- DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
- << "********** Function: "
- << ((Value*)mf_->getFunction())->getName() << '\n';
-
+ DEBUG(errs() << "********** COMPUTING LIVE INTERVALS **********\n"
+ << "********** Function: "
+ << ((Value*)mf_->getFunction())->getName() << '\n');
+
+ SmallVector<unsigned, 8> UndefUses;
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
// Track the index of the current machine instr.
unsigned MIIndex = getMBBStartIdx(MBB);
- DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
+ DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
// Handle defs.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.getReg())
+ continue;
+
// handle register defs - build intervals
- if (MO.isReg() && MO.getReg() && MO.isDef()) {
+ if (MO.isDef())
handleRegisterDef(MBB, MI, MIIndex, MO, i);
- }
+ else if (MO.isUndef())
+ UndefUses.push_back(MO.getReg());
}
// Skip over the empty slots after each instruction.
MIIndex += InstrSlots::NUM;
}
}
+
+ // Create empty intervals for registers defined by implicit_def's (except
+ // for those implicit_def that define values which are liveout of their
+ // blocks.
+ for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
+ unsigned UndefReg = UndefUses[i];
+ (void)getOrCreateInterval(UndefReg);
+ }
}
bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
/// managing the allocated memory.
LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
LiveInterval *NewLI = createInterval(li->reg);
- NewLI->Copy(*li, getVNInfoAllocator());
+ NewLI->Copy(*li, mri_, getVNInfoAllocator());
return NewLI;
}
/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
/// copy field and returns the source register that defines it.
unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
- if (!VNI->copy)
+ if (!VNI->getCopy())
return 0;
- if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
+ if (VNI->getCopy()->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
// If it's extracting out of a physical register, return the sub-register.
- unsigned Reg = VNI->copy->getOperand(1).getReg();
+ unsigned Reg = VNI->getCopy()->getOperand(1).getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg))
- Reg = tri_->getSubReg(Reg, VNI->copy->getOperand(2).getImm());
+ Reg = tri_->getSubReg(Reg, VNI->getCopy()->getOperand(2).getImm());
return Reg;
- } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
- return VNI->copy->getOperand(2).getReg();
+ } else if (VNI->getCopy()->getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ VNI->getCopy()->getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
+ return VNI->getCopy()->getOperand(2).getReg();
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ if (tii_->isMoveInstr(*VNI->getCopy(), SrcReg, DstReg, SrcSubReg, DstSubReg))
return SrcReg;
- assert(0 && "Unrecognized copy instruction!");
+ llvm_unreachable("Unrecognized copy instruction!");
return 0;
}
unsigned Reg = MO.getReg();
if (Reg == 0 || Reg == li.reg)
continue;
+
+ if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ !allocatableRegs_[Reg])
+ continue;
// FIXME: For now, only remat MI with at most one register operand.
assert(!RegOp &&
"Can't rematerialize instruction with multiple register operand!");
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
i != e; ++i) {
const VNInfo *VNI = *i;
- unsigned DefIdx = VNI->def;
- if (DefIdx == ~1U)
+ if (VNI->isUnused())
continue; // Dead val#.
// Is the def for the val# rematerializable?
- if (DefIdx == ~0u)
+ if (!VNI->isDefAccurate())
return false;
- MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx);
+ MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
bool DefIsLoad = false;
if (!ReMatDefMI ||
!isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
const MachineLoopInfo *loopInfo,
unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
- MachineBasicBlock *MBB = MI->getParent();
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
+ std::vector<LiveInterval*> &NewLIs) {
bool CanFold = false;
RestartInstruction:
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
continue;
if (RegJ == RegI) {
Ops.push_back(j);
- HasUse |= MOj.isUse();
- HasDef |= MOj.isDef();
+ if (!MOj.isUndef()) {
+ HasUse |= MOj.isUse();
+ HasDef |= MOj.isDef();
+ }
}
}
- if (HasUse && !li.liveAt(getUseIndex(index)))
- // Must be defined by an implicit def. It should not be spilled. Note,
- // this is for correctness reason. e.g.
- // 8 %reg1024<def> = IMPLICIT_DEF
- // 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
- // The live range [12, 14) are not part of the r1024 live interval since
- // it's defined by an implicit def. It will not conflicts with live
- // interval of r1025. Now suppose both registers are spilled, you can
- // easily see a situation where both registers are reloaded before
- // the INSERT_SUBREG and both target registers that would overlap.
- HasUse = false;
-
- // Update stack slot spill weight if we are splitting.
- float Weight = getSpillWeight(HasDef, HasUse, loopDepth);
- if (!TrySplit)
- SSWeight += Weight;
-
// Create a new virtual register for the spill interval.
// Create the new register now so we can map the fold instruction
// to the new register so when it is unfolded we get the correct
HasUse = false;
HasDef = false;
CanFold = false;
- if (isRemoved(MI)) {
- SSWeight -= Weight;
+ if (isNotInMIMap(MI))
break;
- }
goto RestartInstruction;
}
} else {
if (CreatedNewVReg) {
if (DefIsReMat) {
- vrm.setVirtIsReMaterialized(NewVReg, ReMatDefMI/*, CanDelete*/);
+ vrm.setVirtIsReMaterialized(NewVReg, ReMatDefMI);
if (ReMatIds[VNI->id] == VirtRegMap::MAX_STACK_SLOT) {
// Each valnum may have its own remat id.
ReMatIds[VNI->id] = vrm.assignVirtReMatId(NewVReg);
if (DefIsReMat && ImpUse)
MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true));
- // create a new register interval for this spill / remat.
+ // Create a new register interval for this spill / remat.
LiveInterval &nI = getOrCreateInterval(NewVReg);
if (CreatedNewVReg) {
NewLIs.push_back(&nI);
if (HasUse) {
if (CreatedNewVReg) {
LiveRange LR(getLoadIndex(index), getUseIndex(index)+1,
- nI.getNextValue(~0U, 0, VNInfoAllocator));
+ nI.getNextValue(0, 0, false, VNInfoAllocator));
DOUT << " +" << LR;
nI.addRange(LR);
} else {
}
if (HasDef) {
LiveRange LR(getDefIndex(index), getStoreIndex(index),
- nI.getNextValue(~0U, 0, VNInfoAllocator));
+ nI.getNextValue(0, 0, false, VNInfoAllocator));
DOUT << " +" << LR;
nI.addRange(LR);
}
MachineBasicBlock *MBB, unsigned Idx) const {
unsigned End = getMBBEndIdx(MBB);
for (unsigned j = 0, ee = VNI->kills.size(); j != ee; ++j) {
- unsigned KillIdx = VNI->kills[j];
+ if (VNI->kills[j].isPHIKill)
+ continue;
+
+ unsigned KillIdx = VNI->kills[j].killIdx;
if (KillIdx > Idx && KillIdx < End)
return true;
}
BitVector &RestoreMBBs,
DenseMap<unsigned, std::vector<SRInfo> > &RestoreIdxes,
DenseMap<unsigned,unsigned> &MBBVRegsMap,
- std::vector<LiveInterval*> &NewLIs, float &SSWeight) {
+ std::vector<LiveInterval*> &NewLIs) {
bool AllCanFold = true;
unsigned NewVReg = 0;
unsigned start = getBaseIndex(I->start);
unsigned index = getInstructionIndex(MI);
if (index < start || index >= end)
continue;
- if (O.isUse() && !li.liveAt(getUseIndex(index)))
+
+ if (O.isUndef())
// Must be defined by an implicit def. It should not be spilled. Note,
// this is for correctness reason. e.g.
// 8 %reg1024<def> = IMPLICIT_DEF
index, end, MI, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg,
- ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight);
+ ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs);
if (!HasDef && !HasUse)
continue;
NewLIs.push_back(&getOrCreateInterval(NewVReg));
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.getReg() == li.reg)
+ if (MO.isReg() && MO.getReg() == li.reg) {
MO.setReg(NewVReg);
+ MO.setIsUndef();
+ }
}
}
}
}
-namespace {
- struct LISorter {
- bool operator()(LiveInterval* A, LiveInterval* B) {
- return A->beginNumber() < B->beginNumber();
- }
- };
-}
-
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpillsFast(const LiveInterval &li,
const MachineLoopInfo *loopInfo,
- VirtRegMap &vrm, float& SSWeight) {
+ VirtRegMap &vrm) {
unsigned slot = vrm.assignVirt2StackSlot(li.reg);
std::vector<LiveInterval*> added;
const TargetRegisterClass* rc = mri_->getRegClass(li.reg);
- SSWeight = 0.0f;
-
MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg);
while (RI != mri_->reg_end()) {
MachineInstr* MI = &*RI;
unsigned index = getInstructionIndex(MI);
if (HasUse) {
LiveRange LR(getLoadIndex(index), getUseIndex(index),
- nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ nI.getNextValue(0, 0, false, getVNInfoAllocator()));
DOUT << " +" << LR;
nI.addRange(LR);
vrm.addRestorePoint(NewVReg, MI);
}
if (HasDef) {
LiveRange LR(getDefIndex(index), getStoreIndex(index),
- nI.getNextValue(~0U, 0, getVNInfoAllocator()));
+ nI.getNextValue(0, 0, false, getVNInfoAllocator()));
DOUT << " +" << LR;
nI.addRange(LR);
vrm.addSpillPoint(NewVReg, true, MI);
DOUT << "\t\t\t\tadded new interval: ";
DEBUG(nI.dump());
DOUT << '\n';
-
- unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
- if (HasUse) {
- if (HasDef)
- SSWeight += getSpillWeight(true, true, loopDepth);
- else
- SSWeight += getSpillWeight(false, true, loopDepth);
- } else
- SSWeight += getSpillWeight(true, false, loopDepth);
}
RI = mri_->reg_begin(li.reg);
}
- // Clients expect the new intervals to be returned in sorted order.
- std::sort(added.begin(), added.end(), LISorter());
-
return added;
}
std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li,
SmallVectorImpl<LiveInterval*> &SpillIs,
- const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
- float &SSWeight) {
+ const MachineLoopInfo *loopInfo, VirtRegMap &vrm) {
if (EnableFastSpilling)
- return addIntervalsForSpillsFast(li, loopInfo, vrm, SSWeight);
+ return addIntervalsForSpillsFast(li, loopInfo, vrm);
assert(li.weight != HUGE_VALF &&
"attempt to spill already spilled interval!");
li.print(DOUT, tri_);
DOUT << '\n';
- // Spill slot weight.
- SSWeight = 0.0f;
-
// Each bit specify whether a spill is required in the MBB.
BitVector SpillMBBs(mf_->getNumBlockIDs());
DenseMap<unsigned, std::vector<SRInfo> > SpillIdxes;
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
} else {
rewriteInstructionsForSpills(li, false, I, NULL, 0,
Slot, 0, false, false, false,
false, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
}
IsFirstRange = false;
}
- SSWeight = 0.0f; // Already accounted for when split.
handleSpilledImpDefs(li, vrm, rc, NewLIs);
return NewLIs;
}
i != e; ++i) {
const VNInfo *VNI = *i;
unsigned VN = VNI->id;
- unsigned DefIdx = VNI->def;
- if (DefIdx == ~1U)
+ if (VNI->isUnused())
continue; // Dead val#.
// Is the def for the val# rematerializable?
- MachineInstr *ReMatDefMI = (DefIdx == ~0u)
- ? 0 : getInstructionFromIndex(DefIdx);
+ MachineInstr *ReMatDefMI = VNI->isDefAccurate()
+ ? getInstructionFromIndex(VNI->def) : 0;
bool dummy;
if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, SpillIs, dummy)) {
// Remember how to remat the def of this val#.
ReMatDefs[VN] = Clone;
bool CanDelete = true;
- if (VNI->hasPHIKill) {
+ if (VNI->hasPHIKill()) {
// A kill is a phi node, not all of its uses can be rematerialized.
// It must not be deleted.
CanDelete = false;
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, rc, ReMatIds, loopInfo,
SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
- MBBVRegsMap, NewLIs, SSWeight);
+ MBBVRegsMap, NewLIs);
}
// Insert spills / restores if we are splitting.
if (NeedStackSlot) {
int Id = SpillMBBs.find_first();
while (Id != -1) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
std::vector<SRInfo> &spills = SpillIdxes[Id];
for (unsigned i = 0, e = spills.size(); i != e; ++i) {
int index = spills[i].index;
if (isKill)
AddedKill.insert(&nI);
}
-
- // Update spill slot weight.
- if (!isReMat)
- SSWeight += getSpillWeight(true, false, loopDepth);
}
Id = SpillMBBs.find_next(Id);
}
int Id = RestoreMBBs.find_first();
while (Id != -1) {
- MachineBasicBlock *MBB = mf_->getBlockNumbered(Id);
- unsigned loopDepth = loopInfo->getLoopDepth(MBB);
-
std::vector<SRInfo> &restores = RestoreIdxes[Id];
for (unsigned i = 0, e = restores.size(); i != e; ++i) {
int index = restores[i].index;
nI.removeRange(getLoadIndex(index), getUseIndex(index)+1);
else
vrm.addRestorePoint(VReg, MI);
-
- // Update spill slot weight.
- if (!isReMat)
- SSWeight += getSpillWeight(false, true, loopDepth);
}
Id = RestoreMBBs.find_next(Id);
}
// If there are registers which alias PhysReg, but which are not a
// sub-register of the chosen representative super register. Assert
// since we can't handle it yet.
- assert(*AS == SpillReg || !allocatableRegs_[*AS] ||
+ assert(*AS == SpillReg || !allocatableRegs_[*AS] || !hasInterval(*AS) ||
tri_->isSuperRegister(*AS, SpillReg));
bool Cut = false;
pli.removeRange(StartIdx, EndIdx);
Cut = true;
} else {
- cerr << "Ran out of registers during register allocation!\n";
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Ran out of registers during register allocation!";
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
- cerr << "Please check your inline asm statement for invalid "
+ Msg << "\nPlease check your inline asm statement for invalid "
<< "constraints:\n";
- MI->print(cerr.stream(), tm_);
+ MI->print(Msg, tm_);
}
- exit(1);
+ llvm_report_error(Msg.str());
}
for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) {
if (!hasInterval(*AS))
}
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
- MachineInstr* startInst) {
+ MachineInstr* startInst) {
LiveInterval& Interval = getOrCreateInterval(reg);
VNInfo* VN = Interval.getNextValue(
getInstructionIndex(startInst) + InstrSlots::DEF,
- startInst, getVNInfoAllocator());
- VN->hasPHIKill = true;
- VN->kills.push_back(getMBBEndIdx(startInst->getParent()));
+ startInst, true, getVNInfoAllocator());
+ VN->setHasPHIKill(true);
+ VN->kills.push_back(
+ VNInfo::KillInfo(terminatorGaps[startInst->getParent()], true));
LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF,
getMBBEndIdx(startInst->getParent()) + 1, VN);
Interval.addRange(LR);
return LR;
}
+
+raw_ostream &
+IntervalPrefixPrinter::operator()(raw_ostream &out,
+ const MachineInstr &instr) const {
+ return out << liinfo.getInstructionIndex(&instr);
+}
projects / oota-llvm.git / blobdiff