Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not

[oota-llvm.git] / lib / CodeGen / LiveIntervalAnalysis.h

diff --git a/lib/CodeGen/LiveIntervalAnalysis.h b/lib/CodeGen/LiveIntervalAnalysis.h
index b90be6270418d5a6ba42c54f7b73966b6a35c1a9..f7f4569cb3518b05f08268bd8311d03642bf8014 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.h
+++ b/lib/CodeGen/LiveIntervalAnalysis.h
@@ -28,12 +28,14 @@ namespace llvm {
 
   class LiveVariables;
   class MRegisterInfo;
+  class TargetInstrInfo;
   class VirtRegMap;
 
   class LiveIntervals : public MachineFunctionPass {
     MachineFunction* mf_;
     const TargetMachine* tm_;
     const MRegisterInfo* mri_;
+    const TargetInstrInfo* tii_;
     LiveVariables* lv_;
 
     typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
@@ -81,8 +83,10 @@ namespace llvm {
       return getBaseIndex(index) + InstrSlots::STORE;
     }
 
-    // FIXME: this should really be a const_iterator
     typedef Reg2IntervalMap::iterator iterator;
+    typedef Reg2IntervalMap::const_iterator const_iterator;
+    const_iterator begin() const { return r2iMap_.begin(); }
+    const_iterator end() const { return r2iMap_.end(); }
     iterator begin() { return r2iMap_.begin(); }
     iterator end() { return r2iMap_.end(); }
     unsigned getNumIntervals() const { return r2iMap_.size(); }
@@ -125,6 +129,9 @@ namespace llvm {
     /// runOnMachineFunction - pass entry point
     virtual bool runOnMachineFunction(MachineFunction&);
 
+    /// print - Implement the dump method.
+    virtual void print(std::ostream &O, const Module* = 0) const;
+
   private:
     /// computeIntervals - compute live intervals
     void computeIntervals();
@@ -149,11 +156,15 @@ namespace llvm {
                                   MachineBasicBlock::iterator mi,
                                   LiveInterval& interval);
 
-    /// handlePhysicalRegisterDef - update intervals for a
-    /// physical register def
+    /// handlePhysicalRegisterDef - update intervals for a physical register
+    /// def.  If the defining instruction is a move instruction, SrcReg will be
+    /// the input register, and DestReg will be the result.  Note that Interval
+    /// may not match DestReg (it might be an alias instead).
+    ///
     void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
                                    MachineBasicBlock::iterator mi,
-                                   LiveInterval& interval);
+                                   LiveInterval& interval,
+                                   unsigned SrcReg, unsigned DestReg);
 
     /// Return true if the two specified registers belong to different
     /// register classes.  The registers may be either phys or virt regs.