Fix GCC warning:

[oota-llvm.git] / lib / CodeGen / LiveIntervalUnion.cpp

diff --git a/lib/CodeGen/LiveIntervalUnion.cpp b/lib/CodeGen/LiveIntervalUnion.cpp
index 4b9a2d302c09cd2e7de8cdef47e13bc8b2a95578..cec68850fa884da856d789939e93bedb098d73c9 100644 (file)
--- a/lib/CodeGen/LiveIntervalUnion.cpp
+++ b/lib/CodeGen/LiveIntervalUnion.cpp
@@ -16,9 +16,11 @@
 #define DEBUG_TYPE "regalloc"
 #include "LiveIntervalUnion.h"
 #include "llvm/ADT/SparseBitVector.h"
+#include "llvm/CodeGen/MachineLoopRanges.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include <algorithm>
+#include "llvm/Target/TargetRegisterInfo.h"
+
 using namespace llvm;
 
 
@@ -66,22 +68,37 @@ void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
 }
 
 void
-LiveIntervalUnion::print(raw_ostream &OS,
-                         const AbstractRegisterDescription *RegDesc) const {
+LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
   OS << "LIU ";
-  if (RegDesc != NULL)
-    OS << RegDesc->getName(RepReg);
-  else {
-    OS << RepReg;
+  TRI->printReg(RepReg, OS);
+  if (empty()) {
+    OS << " empty\n";
+    return;
   }
-  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI)
-    dbgs() << " [" << SI.start() << ' ' << SI.stop() << "):%reg"
-           << SI.value()->reg;
-  OS << "\n";
+  for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
+    OS << " [" << SI.start() << ' ' << SI.stop() << "):";
+    TRI->printReg(SI.value()->reg, OS);
+  }
+  OS << '\n';
+}
+
+void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
+                                          const TargetRegisterInfo *TRI) const {
+  OS << '[' << start() << ';' << stop() << "):";
+  TRI->printReg(interference()->reg, OS);
 }
 
-void LiveIntervalUnion::dump(const AbstractRegisterDescription *RegDesc) const {
-  print(dbgs(), RegDesc);
+void LiveIntervalUnion::Query::print(raw_ostream &OS,
+                                     const TargetRegisterInfo *TRI) {
+  OS << "Interferences with ";
+  LiveUnion->print(OS, TRI);
+  InterferenceResult IR = firstInterference();
+  while (isInterference(IR)) {
+    OS << "  ";
+    IR.print(OS, TRI);
+    OS << '\n';
+    nextInterference(IR);
+  }
 }
 
 #ifndef NDEBUG
@@ -144,13 +161,32 @@ void LiveIntervalUnion::Query::findIntersection(InterferenceResult &IR) const {
 
 // Find the first intersection, and cache interference info
 // (retain segment iterators into both VirtReg and LiveUnion).
-LiveIntervalUnion::InterferenceResult
+const LiveIntervalUnion::InterferenceResult &
 LiveIntervalUnion::Query::firstInterference() {
-  if (FirstInterference != LiveIntervalUnion::InterferenceResult()) {
+  if (CheckedFirstInterference)
     return FirstInterference;
+  CheckedFirstInterference = true;
+  InterferenceResult &IR = FirstInterference;
+
+  // Quickly skip interference check for empty sets.
+  if (VirtReg->empty() || LiveUnion->empty()) {
+    IR.VirtRegI = VirtReg->end();
+  } else if (VirtReg->beginIndex() < LiveUnion->startIndex()) {
+    // VirtReg starts first, perform double binary search.
+    IR.VirtRegI = VirtReg->find(LiveUnion->startIndex());
+    if (IR.VirtRegI != VirtReg->end())
+      IR.LiveUnionI = LiveUnion->find(IR.VirtRegI->start);
+  } else {
+    // LiveUnion starts first, perform double binary search.
+    IR.LiveUnionI = LiveUnion->find(VirtReg->beginIndex());
+    if (IR.LiveUnionI.valid())
+      IR.VirtRegI = VirtReg->find(IR.LiveUnionI.start());
+    else
+      IR.VirtRegI = VirtReg->end();
   }
-  FirstInterference = InterferenceResult(VirtReg->begin(), LiveUnion->begin());
   findIntersection(FirstInterference);
+  assert((IR.VirtRegI == VirtReg->end() || IR.LiveUnionI.valid())
+         && "Uninitialized iterator");
   return FirstInterference;
 }
 
@@ -202,7 +238,7 @@ collectInterferingVRegs(unsigned MaxInterferingRegs) {
   InterferenceResult IR = firstInterference();
   LiveInterval::iterator VirtRegEnd = VirtReg->end();
   LiveInterval *RecentInterferingVReg = NULL;
-  while (IR.LiveUnionI.valid()) {
+  if (IR.VirtRegI != VirtRegEnd) while (IR.LiveUnionI.valid()) {
     // Advance the union's iterator to reach an unseen interfering vreg.
     do {
       if (IR.LiveUnionI.value() == RecentInterferingVReg)
@@ -230,10 +266,13 @@ collectInterferingVRegs(unsigned MaxInterferingRegs) {
       if (!IR.LiveUnionI.value()->isSpillable())
         SeenUnspillableVReg = true;
 
-      InterferingVRegs.push_back(IR.LiveUnionI.value());
       if (InterferingVRegs.size() == MaxInterferingRegs)
+        // Leave SeenAllInterferences set to false to indicate that at least one
+        // interference exists beyond those we collected.
         return MaxInterferingRegs;
 
+      InterferingVRegs.push_back(IR.LiveUnionI.value());
+
       // Cache the most recent interfering vreg to bypass isSeenInterference.
       RecentInterferingVReg = IR.LiveUnionI.value();
       ++IR.LiveUnionI;
@@ -246,3 +285,30 @@ collectInterferingVRegs(unsigned MaxInterferingRegs) {
   SeenAllInterferences = true;
   return InterferingVRegs.size();
 }
+
+bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
+  // VirtReg is likely live throughout the loop, so start by checking LIU-Loop
+  // overlaps.
+  IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
+    Overlaps(LiveUnion->getMap(), Loop->getMap());
+  if (!Overlaps.valid())
+    return false;
+
+  // The loop is overlapping an LIU assignment. Check VirtReg as well.
+  LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
+
+  for (;;) {
+    if (VRI == VirtReg->end())
+      return false;
+    if (VRI->start < Overlaps.stop())
+      return true;
+
+    Overlaps.advanceTo(VRI->start);
+    if (!Overlaps.valid())
+      return false;
+    if (Overlaps.start() < VRI->end)
+      return true;
+
+    VRI = VirtReg->advanceTo(VRI, Overlaps.start());
+  }
+}