Remove/fix invalid README entries. The well thought out strcpy function doesn't retur...

[oota-llvm.git] / lib / CodeGen / LiveIntervalUnion.h

diff --git a/lib/CodeGen/LiveIntervalUnion.h b/lib/CodeGen/LiveIntervalUnion.h
index 0c9a13a606c7f1c7d7304ee47f5a6c9a87369bce..ff23cf61a3338c16a5d47d5acf54bf1ea569f5d2 100644 (file)
--- a/lib/CodeGen/LiveIntervalUnion.h
+++ b/lib/CodeGen/LiveIntervalUnion.h
@@ -20,21 +20,19 @@
 #include "llvm/ADT/IntervalMap.h"
 #include "llvm/CodeGen/LiveInterval.h"
 
+#include <algorithm>
+
 namespace llvm {
 
+class MachineLoopRange;
+class TargetRegisterInfo;
+
 #ifndef NDEBUG
 // forward declaration
 template <unsigned Element> class SparseBitVector;
 typedef SparseBitVector<128> LiveVirtRegBitSet;
 #endif
 
-/// Abstraction to provide info for the representative register.
-class AbstractRegisterDescription {
-public:
-  virtual const char *getName(unsigned Reg) const = 0;
-  virtual ~AbstractRegisterDescription() {}
-};
-
 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
 inline bool
 overlap(const LiveRange &VRSeg,
@@ -75,7 +73,13 @@ public:
   // by their starting position.
   SegmentIter begin() { return Segments.begin(); }
   SegmentIter end() { return Segments.end(); }
-  bool empty() { return Segments.empty(); }
+  SegmentIter find(SlotIndex x) { return Segments.find(x); }
+  bool empty() const { return Segments.empty(); }
+  SlotIndex startIndex() const { return Segments.start(); }
+
+  // Provide public access to the underlying map to allow overlap iteration.
+  typedef LiveSegments Map;
+  const Map &getMap() { return Segments; }
 
   // Add a live virtual register to this union and merge its segments.
   void unify(LiveInterval &VirtReg);
@@ -83,10 +87,8 @@ public:
   // Remove a live virtual register's segments from this union.
   void extract(LiveInterval &VirtReg);
 
-  void dump(const AbstractRegisterDescription *RegDesc) const;
-
-  // If tri != NULL, use it to decode RepReg
-  void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
+  // Print union, using TRI to translate register names
+  void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
 
 #ifndef NDEBUG
   // Verify the live intervals in this union and add them to the visited set.
@@ -111,6 +113,19 @@ public:
     // Public default ctor.
     InterferenceResult(): VirtRegI(), LiveUnionI() {}
 
+    /// start - Return the start of the current overlap.
+    SlotIndex start() const {
+      return std::max(VirtRegI->start, LiveUnionI.start());
+    }
+
+    /// stop - Return the end of the current overlap.
+    SlotIndex stop() const {
+      return std::min(VirtRegI->end, LiveUnionI.stop());
+    }
+
+    /// interference - Return the register that is interfering here.
+    LiveInterval *interference() const { return LiveUnionI.value(); }
+
     // Note: this interface provides raw access to the iterators because the
     // result has no way to tell if it's valid to dereference them.
 
@@ -126,6 +141,8 @@ public:
     bool operator!=(const InterferenceResult &IR) const {
       return !operator==(IR);
     }
+
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
   };
 
   /// Query interferences between a single live virtual register and a live
@@ -135,6 +152,7 @@ public:
     LiveInterval *VirtReg;
     InterferenceResult FirstInterference;
     SmallVector<LiveInterval*,4> InterferingVRegs;
+    bool CheckedFirstInterference;
     bool SeenAllInterferences;
     bool SeenUnspillableVReg;
 
@@ -142,24 +160,22 @@ public:
     Query(): LiveUnion(), VirtReg() {}
 
     Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
-      LiveUnion(LIU), VirtReg(VReg), SeenAllInterferences(false),
-      SeenUnspillableVReg(false)
+      LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
+      SeenAllInterferences(false), SeenUnspillableVReg(false)
     {}
 
     void clear() {
       LiveUnion = NULL;
       VirtReg = NULL;
-      FirstInterference = InterferenceResult();
       InterferingVRegs.clear();
+      CheckedFirstInterference = false;
       SeenAllInterferences = false;
       SeenUnspillableVReg = false;
     }
 
     void init(LiveInterval *VReg, LiveIntervalUnion *LIU) {
-      if (VirtReg == VReg) {
-        // We currently allow query objects to be reused acrossed live virtual
-        // registers, but always for the same live interval union.
-        assert(LiveUnion == LIU && "inconsistent initialization");
+      assert(VReg && LIU && "Invalid arguments");
+      if (VirtReg == VReg && LiveUnion == LIU) {
         // Retain cached results, e.g. firstInterference.
         return;
       }
@@ -187,7 +203,7 @@ public:
 
     // Get the first pair of interfering segments, or a noninterfering result.
     // This initializes the firstInterference_ cache.
-    InterferenceResult firstInterference();
+    const InterferenceResult &firstInterference();
 
     // Treat the result as an iterator and advance to the next interfering pair
     // of segments. Visiting each unique interfering pairs means that the same
@@ -212,6 +228,11 @@ public:
       return InterferingVRegs;
     }
 
+    /// checkLoopInterference - Return true if there is interference overlapping
+    /// Loop.
+    bool checkLoopInterference(MachineLoopRange*);
+
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
   private:
     Query(const Query&);          // DO NOT IMPLEMENT
     void operator=(const Query&); // DO NOT IMPLEMENT