static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
-/// getIndexMachineBasicBlock() - Given a block index, return the
-/// MachineBasicBlock corresponding to it.
-MachineBasicBlock *LiveVariables::getIndexMachineBasicBlock(unsigned Idx) {
- if (BBIdxMap.empty()) {
- BBIdxMap.resize(BBMap.size());
- for (std::map<MachineBasicBlock*, unsigned>::iterator I = BBMap.begin(),
- E = BBMap.end(); I != E; ++I) {
- assert(BBIdxMap.size() > I->second && "Indices are not sequential");
- assert(BBIdxMap[I->second] == 0 && "Multiple idx collision!");
- BBIdxMap[I->second] = I->first;
- }
- }
- assert(Idx < BBIdxMap.size() && "BB Index out of range!");
- return BBIdxMap[Idx];
-}
-
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
"getVarInfo: not a virtual register!");
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
- MachineBasicBlock *MBB) {
- unsigned BBNum = getMachineBasicBlockIndex(MBB);
+ MachineBasicBlock *MBB) {
+ unsigned BBNum = MBB->getNumber();
// Check to see if this basic block is one of the killing blocks. If so,
// remove it...
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- if (VRInfo.Kills[i].first == MBB) {
+ if (VRInfo.Kills[i]->getParent() == MBB) {
VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
break;
}
- if (MBB == VRInfo.DefBlock) return; // Terminate recursion
+ if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
if (VRInfo.AliveBlocks.size() <= BBNum)
VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
}
void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
- MachineInstr *MI) {
+ MachineInstr *MI) {
// Check to see if this basic block is already a kill block...
- if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
+ if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the
// live range by updating the kill instruction.
- VRInfo.Kills.back().second = MI;
+ VRInfo.Kills.back() = MI;
return;
}
#ifndef NDEBUG
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
+ assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
+ assert(MBB != VRInfo.DefInst->getParent() &&
+ "Should have kill for defblock!");
// Add a new kill entry for this basic block.
- VRInfo.Kills.push_back(std::make_pair(MBB, MI));
+ VRInfo.Kills.push_back(MI);
// Update all dominating blocks to mark them known live.
const BasicBlock *BB = MBB->getBasicBlock();
if (PhysRegUsed[Alias])
RegistersKilled.insert(std::make_pair(LastUse, Alias));
else
- RegistersDead.insert(std::make_pair(LastUse, Alias));
+ RegistersDead.insert(std::make_pair(LastUse, Alias));
}
PhysRegInfo[Alias] = MI;
PhysRegUsed[Alias] = false;
}
bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
- const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
RegInfo = MF.getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
}
- // Build BBMap...
- unsigned BBNum = 0;
- for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
- BBMap[I] = BBNum++;
-
// PhysRegInfo - Keep track of which instruction was the last use of a
// physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks.
// nodes, which are treated as a special case).
//
MachineBasicBlock *Entry = MF.begin();
- for (df_iterator<MachineBasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
- DFI != E; ++DFI) {
+ std::set<MachineBasicBlock*> Visited;
+ for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
+ E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
MachineBasicBlock *MBB = *DFI;
- unsigned BBNum = getMachineBasicBlockIndex(MBB);
+ unsigned BBNum = MBB->getNumber();
// Loop over all of the instructions, processing them.
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
- I != E; ++I) {
+ I != E; ++I) {
MachineInstr *MI = I;
const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks.
if (MI->getOpcode() == TargetInstrInfo::PHI)
- NumOperandsToProcess = 1;
+ NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
for (const unsigned *ImplicitUses = MID.ImplicitUses;
*ImplicitUses; ++ImplicitUses)
- HandlePhysRegUse(*ImplicitUses, MI);
+ HandlePhysRegUse(*ImplicitUses, MI);
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isUse() && MO.isRegister() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())){
- HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isUse() && MO.isRegister() && MO.getReg()) {
+ if (MRegisterInfo::isVirtualRegister(MO.getReg())){
+ HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
+ } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
- HandlePhysRegUse(MO.getReg(), MI);
- }
- }
+ HandlePhysRegUse(MO.getReg(), MI);
+ }
+ }
}
// Loop over implicit defs, defining them.
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isDef() && MO.isRegister() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
- VarInfo &VRInfo = getVarInfo(MO.getReg());
-
- assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
- VRInfo.DefBlock = MBB; // Created here...
- VRInfo.DefInst = MI;
- VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isDef() && MO.isRegister() && MO.getReg()) {
+ if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ VarInfo &VRInfo = getVarInfo(MO.getReg());
+
+ assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
+ VRInfo.DefInst = MI;
+ // Defaults to dead
+ VRInfo.Kills.push_back(MI);
+ } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
- HandlePhysRegDef(MO.getReg(), MI);
- }
- }
+ HandlePhysRegDef(MO.getReg(), MI);
+ }
+ }
}
}
// PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
- MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
- for (unsigned i = 1; ; i += 2) {
+ MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
+ for (unsigned i = 1; ; i += 2) {
assert(MI->getNumOperands() > i+1 &&
"Didn't find an entry for our predecessor??");
- if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.getVRegValueOrNull()) {
- VarInfo &VRInfo = getVarInfo(MO.getReg());
-
- // Only mark it alive only in the block we are representing...
- MarkVirtRegAliveInBlock(VRInfo, MBB);
- break; // Found the PHI entry for this block...
- }
- }
+ if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.getVRegValueOrNull()) {
+ VarInfo &VRInfo = getVarInfo(MO.getReg());
+
+ // Only mark it alive only in the block we are representing...
+ MarkVirtRegAliveInBlock(VRInfo, MBB);
+ break; // Found the PHI entry for this block...
+ }
+ }
}
}
}
// end of the basic block. This also resets the PhysRegInfo map.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
if (PhysRegInfo[i])
- HandlePhysRegDef(i, 0);
+ HandlePhysRegDef(i, 0);
}
// Convert the information we have gathered into VirtRegInfo and transform it
//
for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
- if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
- RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
- i + MRegisterInfo::FirstVirtualRegister));
+ if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
+ RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j],
+ i + MRegisterInfo::FirstVirtualRegister));
else
- RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
- i + MRegisterInfo::FirstVirtualRegister));
+ RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j],
+ i + MRegisterInfo::FirstVirtualRegister));
}
-
+
+ // Check to make sure there are no unreachable blocks in the MC CFG for the
+ // function. If so, it is due to a bug in the instruction selector or some
+ // other part of the code generator if this happens.
+#ifndef NDEBUG
+ for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ assert(Visited.count(&*i) != 0 && "unreachable basic block found");
+#endif
+
return false;
}
RegistersKilled.insert(std::make_pair(NewMI, Regs[i]));
Regs.clear();
-
// Move the dead information over...
tie(I, E) = dead_range(OldMI);
for (killed_iterator A = I; A != E; ++A)
projects / oota-llvm.git / blobdiff