for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isKill()) {
- if (RegInfo->regsOverlap(Reg, MO.getReg()))
+ if ((MO.getReg() == Reg) ||
+ (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
}
}
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead())
- if (RegInfo->regsOverlap(Reg, MO.getReg()))
+ if (MO.isReg() && MO.isDead()) {
+ if ((MO.getReg() == Reg) ||
+ (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+ MRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MO.getReg(), Reg)))
return true;
+ }
}
return false;
}
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
- if (RegInfo->regsOverlap(Reg, MO.getReg()))
- return true;
- }
+ if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+ return true;
}
return false;
}
MarkVirtRegAliveInBlock(VRInfo, *PI);
}
-void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
+bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
+ bool AddIfNotFound) {
+ bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
- MO.setIsKill();
- break;
+ if (MO.isReg() && MO.isUse()) {
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ if (Reg == IncomingReg) {
+ MO.setIsKill();
+ Found = true;
+ break;
+ } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
+ MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ RegInfo->isSuperRegister(IncomingReg, Reg) &&
+ MO.isKill())
+ // A super-register kill already exists.
+ return true;
}
}
+
+ // If not found, this means an alias of one of the operand is killed. Add a
+ // new implicit operand if required.
+ if (!Found && AddIfNotFound) {
+ MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ return true;
+ }
+ return Found;
}
-void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
+bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
+ bool AddIfNotFound) {
+ bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
- MO.setIsDead();
- break;
+ if (MO.isReg() && MO.isDef()) {
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ if (Reg == IncomingReg) {
+ MO.setIsDead();
+ Found = true;
+ break;
+ } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
+ MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+ RegInfo->isSuperRegister(IncomingReg, Reg) &&
+ MO.isDead())
+ // There exists a super-register that's marked dead.
+ return true;
}
}
+
+ // If not found, this means an alias of one of the operand is dead. Add a
+ // new implicit operand.
+ if (!Found && AddIfNotFound) {
+ MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
+ true/*IsDead*/);
+ return true;
+ }
+ return Found;
}
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
+ // There is a now a proper use, forget about the last partial use.
+ PhysRegPartUse[Reg] = NULL;
+
+ // Turn previous partial def's into read/mod/write.
+ for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
+ MachineInstr *Def = PhysRegPartDef[Reg][i];
+ // First one is just a def. This means the use is reading some undef bits.
+ if (i != 0)
+ Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ }
+ PhysRegPartDef[Reg].clear();
+
+ // There was an earlier def of a super-register. Add implicit def to that MI.
+ // A: EAX = ...
+ // B: = AX
+ // Add implicit def to A.
+ if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
+ MachineInstr *Def = PhysRegInfo[Reg];
+ if (!Def->findRegisterDefOperand(Reg))
+ Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ }
+
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- unsigned Alias = *AliasSet; ++AliasSet) {
- PhysRegInfo[Alias] = MI;
- PhysRegUsed[Alias] = true;
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ PhysRegInfo[SubReg] = MI;
+ PhysRegUsed[SubReg] = true;
}
+
+ // Remember the partial uses.
+ for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
+ unsigned SuperReg = *SuperRegs; ++SuperRegs)
+ PhysRegPartUse[SuperReg] = MI;
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
// Does this kill a previous version of this register?
- if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
+ if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
if (PhysRegUsed[Reg])
- addRegisterKilled(Reg, LastUse);
+ addRegisterKilled(Reg, LastRef);
+ else if (PhysRegPartUse[Reg])
+ // Add implicit use / kill to last use of a sub-register.
+ addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
else
- addRegisterDead(Reg, LastUse);
+ addRegisterDead(Reg, LastRef);
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
-
- for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
- unsigned Alias = *AliasSet; ++AliasSet) {
- if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
- if (PhysRegUsed[Alias])
- addRegisterKilled(Alias, LastUse);
+ PhysRegPartUse[Reg] = NULL;
+
+ for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs) {
+ if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
+ if (PhysRegUsed[SubReg])
+ addRegisterKilled(SubReg, LastRef);
+ else if (PhysRegPartUse[SubReg])
+ // Add implicit use / kill to last use of a sub-register.
+ addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
else
- addRegisterDead(Alias, LastUse);
+ addRegisterDead(SubReg, LastRef);
}
- PhysRegInfo[Alias] = MI;
- PhysRegUsed[Alias] = false;
+ PhysRegInfo[SubReg] = MI;
+ PhysRegUsed[SubReg] = false;
+ }
+
+ if (MI)
+ for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
+ unsigned SuperReg = *SuperRegs; ++SuperRegs) {
+ if (PhysRegInfo[SuperReg]) {
+ // The larger register is previously defined. Now a smaller part is
+ // being re-defined. Treat it as read/mod/write.
+ // EAX =
+ // AX = EAX<imp-use,kill>, EAX<imp-def>
+ MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
+ MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
+ PhysRegInfo[SuperReg] = MI;
+ PhysRegUsed[SuperReg] = false;
+ } else {
+ // Remember this partial def.
+ PhysRegPartDef[SuperReg].push_back(MI);
+ }
}
}
ReservedRegisters = RegInfo->getReservedRegs(mf);
- // PhysRegInfo - Keep track of which instruction was the last use of a
- // physical register. This is a purely local property, because all physical
- // register references as presumed dead across basic blocks.
- //
- PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
- RegInfo->getNumRegs());
- PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
- std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
+ unsigned NumRegs = RegInfo->getNumRegs();
+ PhysRegInfo = new MachineInstr*[NumRegs];
+ PhysRegUsed = new bool[NumRegs];
+ PhysRegPartUse = new MachineInstr*[NumRegs];
+ PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
+ PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
+ std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
+ std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
+ std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
/// Get some space for a respectable number of registers...
VirtRegInfo.resize(64);
// bottom of this basic block. We check all of our successor blocks to see
// if they have PHI nodes, and if so, we simulate an assignment at the end
// of the current block.
- if (!PHIVarInfo[MBB].empty()) {
- std::vector<unsigned>& VarInfoVec = PHIVarInfo[MBB];
+ if (!PHIVarInfo[MBB->getNumber()].empty()) {
+ SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
- for (std::vector<unsigned>::iterator I = VarInfoVec.begin(),
+ for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
E = VarInfoVec.end(); I != E; ++I) {
VarInfo& VRInfo = getVarInfo(*I);
assert(VRInfo.DefInst && "Register use before def (or no def)!");
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
// Add live-out registers as implicit uses.
- Ret->addRegOperand(*I, false, true);
+ if (Ret->findRegisterUseOperandIdx(*I) == -1)
+ Ret->addRegOperand(*I, false, true);
}
}
// Loop over PhysRegInfo, killing any registers that are available at the
// end of the basic block. This also resets the PhysRegInfo map.
- for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
+ for (unsigned i = 0; i != NumRegs; ++i)
if (PhysRegInfo[i])
HandlePhysRegDef(i, 0);
+
+ // Clear some states between BB's. These are purely local information.
+ for (unsigned i = 0; i != NumRegs; ++i)
+ PhysRegPartDef[i].clear();
+ std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
}
// Convert and transfer the dead / killed information we have gathered into
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif
- PHIVarInfo.clear();
+ delete[] PhysRegInfo;
+ delete[] PhysRegUsed;
+ delete[] PhysRegPartUse;
+ delete[] PhysRegPartDef;
+ delete[] PHIVarInfo;
+
return false;
}
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()].
+ PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
push_back(BBI->getOperand(i).getReg());
}
projects / oota-llvm.git / blobdiff