//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/DepthFirstIterator.h"
static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
void LiveVariables::VarInfo::dump() const {
- cerr << "Register Defined by: ";
- if (DefInst)
- cerr << *DefInst;
- else
- cerr << "<null>\n";
cerr << " Alive in blocks: ";
for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
if (AliveBlocks[i]) cerr << i << ", ";
+ cerr << " Used in blocks: ";
+ for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
+ if (UsedBlocks[i]) cerr << i << ", ";
cerr << "\n Killed by:";
if (Kills.empty())
cerr << " No instructions.\n";
}
}
+/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
- assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
+ assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
"getVarInfo: not a virtual register!");
- RegIdx -= MRegisterInfo::FirstVirtualRegister;
+ RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
if (RegIdx >= VirtRegInfo.size()) {
if (RegIdx >= 2*VirtRegInfo.size())
VirtRegInfo.resize(RegIdx*2);
}
VarInfo &VI = VirtRegInfo[RegIdx];
VI.AliveBlocks.resize(MF->getNumBlockIDs());
+ VI.UsedBlocks.resize(MF->getNumBlockIDs());
return VI;
}
+/// KillsRegister - Returns true if the machine instruction kills the specified
+/// register.
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
- if ((MO.getReg() == Reg) ||
- (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- MRegisterInfo::isPhysicalRegister(Reg) &&
- RegInfo->isSubRegister(MO.getReg(), Reg)))
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister() && MO.isKill()) {
+ unsigned MOReg = MO.getReg();
+ if (MOReg == Reg ||
+ (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MOReg, Reg)))
return true;
}
}
return false;
}
+/// RegisterDefIsDead - Returns true if the register is dead in this machine
+/// instruction.
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
- if ((MO.getReg() == Reg) ||
- (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- MRegisterInfo::isPhysicalRegister(Reg) &&
- RegInfo->isSubRegister(MO.getReg(), Reg)))
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister() && MO.isDead()) {
+ unsigned MOReg = MO.getReg();
+ if ((MOReg == Reg) ||
+ (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ RegInfo->isSubRegister(MOReg, Reg)))
return true;
}
}
return false;
}
+/// ModifiesRegister - Returns true if the machine instruction modifies the
+/// register.
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return true;
}
return false;
}
-void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
+ MachineBasicBlock *DefBlock,
MachineBasicBlock *MBB,
std::vector<MachineBasicBlock*> &WorkList) {
unsigned BBNum = MBB->getNumber();
-
+
// Check to see if this basic block is one of the killing blocks. If so,
- // remove it...
+ // remove it.
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
if (VRInfo.Kills[i]->getParent() == MBB) {
VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
break;
}
-
- if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
+
+ if (MBB == DefBlock) return; // Terminate recursion
if (VRInfo.AliveBlocks[BBNum])
return; // We already know the block is live
}
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
+ MachineBasicBlock *DefBlock,
MachineBasicBlock *MBB) {
std::vector<MachineBasicBlock*> WorkList;
- MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
+ MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
+
while (!WorkList.empty()) {
MachineBasicBlock *Pred = WorkList.back();
WorkList.pop_back();
- MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
+ MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
}
}
-void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
+void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
MachineInstr *MI) {
- assert(VRInfo.DefInst && "Register use before def!");
+ const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
+ assert(MRI.getVRegDef(reg) && "Register use before def!");
+ unsigned BBNum = MBB->getNumber();
+
+ VarInfo& VRInfo = getVarInfo(reg);
+ VRInfo.UsedBlocks[BBNum] = true;
VRInfo.NumUses++;
- // Check to see if this basic block is already a kill block...
+ // Check to see if this basic block is already a kill block.
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
- // Yes, this register is killed in this basic block already. Increase the
+ // Yes, this register is killed in this basic block already. Increase the
// live range by updating the kill instruction.
VRInfo.Kills.back() = MI;
return;
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefInst->getParent() &&
+ assert(MBB != MRI.getVRegDef(reg)->getParent() &&
"Should have kill for defblock!");
- // Add a new kill entry for this basic block.
- // If this virtual register is already marked as alive in this basic block,
- // that means it is alive in at least one of the successor block, it's not
- // a kill.
- if (!VRInfo.AliveBlocks[MBB->getNumber()])
+ // Add a new kill entry for this basic block. If this virtual register is
+ // already marked as alive in this basic block, that means it is alive in at
+ // least one of the successor blocks, it's not a kill.
+ if (!VRInfo.AliveBlocks[BBNum])
VRInfo.Kills.push_back(MI);
- // Update all dominating blocks to mark them known live.
+ // Update all dominating blocks to mark them as "known live".
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
E = MBB->pred_end(); PI != E; ++PI)
- MarkVirtRegAliveInBlock(VRInfo, *PI);
-}
-
-bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
- bool AddIfNotFound) {
- bool Found = false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isUse()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
- MO.setIsKill();
- Found = true;
- break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isKill())
- // A super-register kill already exists.
- return true;
- }
- }
-
- // If not found, this means an alias of one of the operand is killed. Add a
- // new implicit operand if required.
- if (!Found && AddIfNotFound) {
- MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- return true;
- }
- return Found;
-}
-
-bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
- bool AddIfNotFound) {
- bool Found = false;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef()) {
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (Reg == IncomingReg) {
- MO.setIsDead();
- Found = true;
- break;
- } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
- MRegisterInfo::isPhysicalRegister(IncomingReg) &&
- RegInfo->isSuperRegister(IncomingReg, Reg) &&
- MO.isDead())
- // There exists a super-register that's marked dead.
- return true;
- }
- }
-
- // If not found, this means an alias of one of the operand is dead. Add a
- // new implicit operand.
- if (!Found && AddIfNotFound) {
- MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
- true/*IsDead*/);
- return true;
- }
- return Found;
+ MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
}
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
- // There is a now a proper use, forget about the last partial use.
- PhysRegPartUse[Reg] = NULL;
-
// Turn previous partial def's into read/mod/write.
for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
MachineInstr *Def = PhysRegPartDef[Reg][i];
// First one is just a def. This means the use is reading some undef bits.
if (i != 0)
- Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
+ true/*IsImp*/,true/*IsKill*/));
+ Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
}
+
PhysRegPartDef[Reg].clear();
// There was an earlier def of a super-register. Add implicit def to that MI.
// A: EAX = ...
// B: = AX
// Add implicit def to A.
- if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
+ if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
+ !PhysRegUsed[Reg]) {
MachineInstr *Def = PhysRegInfo[Reg];
if (!Def->findRegisterDefOperand(Reg))
- Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
+ Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
+ true/*IsImp*/));
}
+ // There is a now a proper use, forget about the last partial use.
+ PhysRegPartUse[Reg] = NULL;
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
PhysRegUsed[SubReg] = true;
}
- // Remember the partial uses.
for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
- unsigned SuperReg = *SuperRegs; ++SuperRegs)
- PhysRegPartUse[SuperReg] = MI;
+ unsigned SuperReg = *SuperRegs; ++SuperRegs) {
+ // Remember the partial use of this superreg if it was previously defined.
+ bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
+ if (!HasPrevDef) {
+ for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
+ unsigned SSReg = *SSRegs; ++SSRegs) {
+ if (PhysRegInfo[SSReg] != NULL) {
+ HasPrevDef = true;
+ break;
+ }
+ }
+ }
+ if (HasPrevDef) {
+ PhysRegInfo[SuperReg] = MI;
+ PhysRegPartUse[SuperReg] = MI;
+ }
+ }
}
-bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
- SmallSet<unsigned, 4> &SubKills) {
+/// addRegisterKills - For all of a register's sub-registers that are killed in
+/// other instructions (?), indicate that they are killed in this machine
+/// instruction by marking the operand as "killed". (If the machine operand
+/// isn't found, add it first.)
+void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
+ SmallSet<unsigned, 4> &SubKills) {
+ if (SubKills.count(Reg) == 0) {
+ MI->addRegisterKilled(Reg, RegInfo, true);
+ return;
+ }
+
for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs) {
- MachineInstr *LastRef = PhysRegInfo[SubReg];
- if (LastRef != RefMI)
- SubKills.insert(SubReg);
- else if (!HandlePhysRegKill(SubReg, RefMI, SubKills))
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, MI, SubKills);
+}
+
+/// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
+/// if:
+///
+/// - The register has no sub-registers and the machine instruction is the
+/// last def/use of the register, or
+/// - The register has sub-registers and none of them are killed elsewhere.
+///
+bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
+ SmallSet<unsigned, 4> &SubKills) {
+ const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+
+ for (; unsigned SubReg = *SubRegs; ++SubRegs) {
+ const MachineInstr *LastRef = PhysRegInfo[SubReg];
+
+ if (LastRef != RefMI ||
+ !HandlePhysRegKill(SubReg, RefMI, SubKills))
SubKills.insert(SubReg);
}
- if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
+ if (*SubRegs == 0) {
// No sub-registers, just check if reg is killed by RefMI.
if (PhysRegInfo[Reg] == RefMI)
return true;
- } else if (SubKills.empty())
- // None of the sub-registers are killed elsewhere...
+ } else if (SubKills.empty()) {
+ // None of the sub-registers are killed elsewhere.
return true;
- return false;
-}
-
-void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
- SmallSet<unsigned, 4> &SubKills) {
- if (SubKills.count(Reg) == 0)
- addRegisterKilled(Reg, MI, true);
- else {
- for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- addRegisterKills(SubReg, MI, SubKills);
}
+
+ return false;
}
+/// HandlePhysRegKill - Calls the recursive version of HandlePhysRegKill. (See
+/// above for details.)
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
SmallSet<unsigned, 4> SubKills;
+
if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
- addRegisterKilled(Reg, RefMI);
+ // This machine instruction kills this register.
+ RefMI->addRegisterKilled(Reg, RegInfo, true);
return true;
- } else {
- // Some sub-registers are killed by another MI.
- for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
- unsigned SubReg = *SubRegs; ++SubRegs)
- addRegisterKills(SubReg, RefMI, SubKills);
- return false;
}
+
+ // Some sub-registers are killed by another machine instruction.
+ for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ addRegisterKills(SubReg, RefMI, SubKills);
+
+ return false;
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
if (PhysRegUsed[Reg]) {
if (!HandlePhysRegKill(Reg, LastRef)) {
if (PhysRegPartUse[Reg])
- addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
+ PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
}
- } else if (PhysRegPartUse[Reg])
- // Add implicit use / kill to last use of a sub-register.
- addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
- else
- addRegisterDead(Reg, LastRef);
+ } else if (PhysRegPartUse[Reg]) {
+ // Add implicit use / kill to last partial use.
+ PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
+ } else if (LastRef != MI) {
+ // Defined, but not used. However, watch out for cases where a super-reg
+ // is also defined on the same MI.
+ LastRef->addRegisterDead(Reg, RegInfo);
+ }
}
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
if (PhysRegUsed[SubReg]) {
if (!HandlePhysRegKill(SubReg, LastRef)) {
if (PhysRegPartUse[SubReg])
- addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
+ PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
}
- } else if (PhysRegPartUse[SubReg])
+ } else if (PhysRegPartUse[SubReg]) {
// Add implicit use / kill to last use of a sub-register.
- addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
- else
- addRegisterDead(SubReg, LastRef);
+ PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
+ } else if (LastRef != MI) {
+ // This must be a def of the subreg on the same MI.
+ LastRef->addRegisterDead(SubReg, RegInfo);
+ }
}
}
if (MI) {
for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
unsigned SuperReg = *SuperRegs; ++SuperRegs) {
- if (PhysRegInfo[SuperReg]) {
+ if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
// The larger register is previously defined. Now a smaller part is
// being re-defined. Treat it as read/mod/write.
// EAX =
// AX = EAX<imp-use,kill>, EAX<imp-def>
- MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
- MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
+ MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
+ true/*IsImp*/,true/*IsKill*/));
+ MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
+ true/*IsImp*/));
PhysRegInfo[SuperReg] = MI;
PhysRegUsed[SuperReg] = false;
PhysRegPartUse[SuperReg] = NULL;
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
+ PhysRegPartDef[Reg].clear();
PhysRegPartUse[Reg] = NULL;
+
for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs) {
PhysRegInfo[SubReg] = MI;
PhysRegUsed[SubReg] = false;
+ PhysRegPartDef[SubReg].clear();
PhysRegPartUse[SubReg] = NULL;
}
}
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
RegInfo = MF->getTarget().getRegisterInfo();
+ MachineRegisterInfo& MRI = mf.getRegInfo();
assert(RegInfo && "Target doesn't have register information?");
ReservedRegisters = RegInfo->getReservedRegs(mf);
// Mark live-in registers as live-in.
for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
EE = MBB->livein_end(); II != EE; ++II) {
- assert(MRegisterInfo::isPhysicalRegister(*II) &&
+ assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
"Cannot have a live-in virtual register!");
HandlePhysRegDef(*II, 0);
}
// Process all uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ const MachineOperand &MO = MI->getOperand(i);
+
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())){
- HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- !ReservedRegisters[MO.getReg()]) {
- HandlePhysRegUse(MO.getReg(), MI);
- }
+ unsigned MOReg = MO.getReg();
+
+ if (TargetRegisterInfo::isVirtualRegister(MOReg))
+ HandleVirtRegUse(MOReg, MBB, MI);
+ else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ !ReservedRegisters[MOReg])
+ HandlePhysRegUse(MOReg, MI);
}
}
// Process all defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ const MachineOperand &MO = MI->getOperand(i);
+
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
- if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
- VarInfo &VRInfo = getVarInfo(MO.getReg());
-
- assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
- VRInfo.DefInst = MI;
- // Defaults to dead
- VRInfo.Kills.push_back(MI);
- } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- !ReservedRegisters[MO.getReg()]) {
- HandlePhysRegDef(MO.getReg(), MI);
+ unsigned MOReg = MO.getReg();
+
+ if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
+ VarInfo &VRInfo = getVarInfo(MOReg);
+
+ if (VRInfo.AliveBlocks.none())
+ // If vr is not alive in any block, then defaults to dead.
+ VRInfo.Kills.push_back(MI);
+ } else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ !ReservedRegisters[MOReg]) {
+ HandlePhysRegDef(MOReg, MI);
}
}
}
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
- E = VarInfoVec.end(); I != E; ++I) {
- VarInfo& VRInfo = getVarInfo(*I);
- assert(VRInfo.DefInst && "Register use before def (or no def)!");
-
- // Only mark it alive only in the block we are representing.
- MarkVirtRegAliveInBlock(VRInfo, MBB);
- }
+ E = VarInfoVec.end(); I != E; ++I)
+ // Mark it alive only in the block we are representing.
+ MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
+ MBB);
}
// Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
- if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
+ if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
MachineInstr *Ret = &MBB->back();
- for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
- E = MF->liveout_end(); I != E; ++I) {
- assert(MRegisterInfo::isPhysicalRegister(*I) &&
+
+ for (MachineRegisterInfo::liveout_iterator
+ I = MF->getRegInfo().liveout_begin(),
+ E = MF->getRegInfo().liveout_end(); I != E; ++I) {
+ assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
+
// Add live-out registers as implicit uses.
if (Ret->findRegisterUseOperandIdx(*I) == -1)
- Ret->addRegOperand(*I, false, true);
+ Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
}
}
// Clear some states between BB's. These are purely local information.
for (unsigned i = 0; i != NumRegs; ++i)
PhysRegPartDef[i].clear();
+
std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
// VirtRegInfo onto MI's.
//
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
- for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
- if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
- addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
- VirtRegInfo[i].Kills[j]);
+ for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
+ if (VirtRegInfo[i].Kills[j] ==
+ MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
+ VirtRegInfo[i]
+ .Kills[j]->addRegisterDead(i +
+ TargetRegisterInfo::FirstVirtualRegister,
+ RegInfo);
else
- addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
- VirtRegInfo[i].Kills[j]);
- }
+ VirtRegInfo[i]
+ .Kills[j]->addRegisterKilled(i +
+ TargetRegisterInfo::FirstVirtualRegister,
+ RegInfo);
// Check to make sure there are no unreachable blocks in the MC CFG for the
// function. If so, it is due to a bug in the instruction selector or some
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OldMI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
- MRegisterInfo::isVirtualRegister(MO.getReg())) {
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);
if (MO.isDef()) {
if (MO.isDead()) {
- MO.unsetIsDead();
+ MO.setIsDead(false);
addVirtualRegisterDead(Reg, NewMI);
}
- // Update the defining instruction.
- if (VI.DefInst == OldMI)
- VI.DefInst = NewMI;
}
if (MO.isKill()) {
- MO.unsetIsKill();
+ MO.setIsKill(false);
addVirtualRegisterKilled(Reg, NewMI);
}
// If this is a kill of the value, update the VI kills list.
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isKill()) {
- MO.unsetIsKill();
+ if (MO.isRegister() && MO.isKill()) {
+ MO.setIsKill(false);
unsigned Reg = MO.getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
}
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead()) {
- MO.unsetIsDead();
+ if (MO.isRegister() && MO.isDead()) {
+ MO.setIsDead(false);
unsigned Reg = MO.getReg();
- if (MRegisterInfo::isVirtualRegister(Reg)) {
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
}
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
- PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
- push_back(BBI->getOperand(i).getReg());
+ PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
+ .push_back(BBI->getOperand(i).getReg());
}
projects / oota-llvm.git / blobdiff