//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
//
-// This file implements the LiveVariable analysis pass.
-//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the LiveVariable analysis pass. For each machine
+// instruction in the function, this pass calculates the set of registers that
+// are immediately dead after the instruction (i.e., the instruction calculates
+// the value, but it is never used) and the set of registers that are used by
+// the instruction, but are never used after the instruction (i.e., they are
+// killed).
+//
+// This class computes live variables using are sparse implementation based on
+// the machine code SSA form. This class computes live variable information for
+// each virtual and _register allocatable_ physical register in a function. It
+// uses the dominance properties of SSA form to efficiently compute live
+// variables for virtual registers, and assumes that physical registers are only
+// live within a single basic block (allowing it to do a single local analysis
+// to resolve physical register lifetimes in each basic block). If a physical
+// register is not register allocatable, it is not tracked. This is useful for
+// things like the stack pointer and condition codes.
+//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/LiveVariables.h"
static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
+const std::pair<MachineBasicBlock*, unsigned> &
+LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{
+ return BBMap.find(MBB->getBasicBlock())->second;
+}
+
+LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
+ assert(RegIdx >= MRegisterInfo::FirstVirtualRegister &&
+ "getVarInfo: not a virtual register!");
+ RegIdx -= MRegisterInfo::FirstVirtualRegister;
+ if (RegIdx >= VirtRegInfo.size()) {
+ if (RegIdx >= 2*VirtRegInfo.size())
+ VirtRegInfo.resize(RegIdx*2);
+ else
+ VirtRegInfo.resize(2*VirtRegInfo.size());
+ }
+ return VirtRegInfo[RegIdx];
+}
+
+
+
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
const BasicBlock *BB) {
const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
if (PhysRegInfo[Reg]) {
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
- for (; unsigned NReg = AliasSet[0]; ++AliasSet)
- if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
- PhysRegInfo[NReg] = MI;
- PhysRegUsed[NReg] = true;
+ } else {
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
+ PhysRegInfo[*AliasSet] = MI;
+ PhysRegUsed[*AliasSet] = true;
}
+ }
}
}
RegistersKilled.insert(std::make_pair(LastUse, Reg));
else
RegistersDead.insert(std::make_pair(LastUse, Reg));
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
- for (; unsigned NReg = AliasSet[0]; ++AliasSet)
- if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
- if (PhysRegUsed[NReg])
- RegistersKilled.insert(std::make_pair(LastUse, NReg));
+ } else {
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
+ if (PhysRegUsed[*AliasSet])
+ RegistersKilled.insert(std::make_pair(LastUse, *AliasSet));
else
- RegistersDead.insert(std::make_pair(LastUse, NReg));
- PhysRegInfo[NReg] = 0; // Kill the aliased register
+ RegistersDead.insert(std::make_pair(LastUse, *AliasSet));
+ PhysRegInfo[*AliasSet] = 0; // Kill the aliased register
}
+ }
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
}
bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
+ // First time though, initialize AllocatablePhysicalRegisters for the target
+ if (AllocatablePhysicalRegisters.empty()) {
+ const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ assert(&MRI && "Target doesn't have register information?");
+
+ // Make space, initializing to false...
+ AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister);
+
+ // Loop over all of the register classes...
+ for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(),
+ E = MRI.regclass_end(); RCI != E; ++RCI)
+ // Loop over all of the allocatable registers in the function...
+ for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
+ E = (*RCI)->allocation_order_end(MF); I != E; ++I)
+ AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
+ }
+
// Build BBMap...
unsigned BBNum = 0;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
- if (const unsigned *ImplicitUses = MID.ImplicitUses)
- for (unsigned i = 0; ImplicitUses[i]; ++i)
- HandlePhysRegUse(ImplicitUses[i], MI);
+ for (const unsigned *ImplicitUses = MID.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ HandlePhysRegUse(*ImplicitUses, MI);
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.opIsUse() || MO.opIsDefAndUse()) {
if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
- unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
- HandleVirtRegUse(getVarInfo(RegIdx), MBB, MI);
- } else if (MO.isPhysicalRegister() && MO.getReg() != 0
- /// FIXME: This is a gross hack, due to us not being able to
- /// say that some registers are defined on entry to the
- /// function. 5 = ESP
-&& MO.getReg() != 5
-) {
+ HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
+ } else if (MO.isPhysicalRegister() &&
+ AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
}
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.opIsDef() || MO.opIsDefAndUse()) {
+ if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
if (MO.isVirtualRegister()) {
- unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
- VarInfo &VRInfo = getVarInfo(RegIdx);
+ VarInfo &VRInfo = getVarInfo(MO.getReg());
assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
VRInfo.DefBlock = MBB; // Created here...
VRInfo.DefInst = MI;
VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
- } else if (MO.isPhysicalRegister() && MO.getReg() != 0
- /// FIXME: This is a gross hack, due to us not being able to
- /// say that some registers are defined on entry to the
- /// function. 5 = ESP
-&& MO.getReg() != 5
-) {
+ } else if (MO.isPhysicalRegister() &&
+ AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}
}
// bottom of this basic block. We check all of our successor blocks to see
// if they have PHI nodes, and if so, we simulate an assignment at the end
// of the current block.
- for (succ_const_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I){
- MachineBasicBlock *Succ = BBMap.find(*I)->second.first;
+ for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB);
+ SI != E; ++SI) {
+ MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
// PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
+ MachineInstr *MI = *I;
for (unsigned i = 1; ; i += 2)
- if ((*I)->getOperand(i+1).getMachineBasicBlock() == MBB) {
- MachineOperand &MO = (*I)->getOperand(i);
+ if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
+ MachineOperand &MO = MI->getOperand(i);
if (!MO.getVRegValueOrNull()) {
- unsigned RegIdx = MO.getReg()-MRegisterInfo::FirstVirtualRegister;
- VarInfo &VRInfo = getVarInfo(RegIdx);
+ VarInfo &VRInfo = getVarInfo(MO.getReg());
// Only mark it alive only in the block we are representing...
MarkVirtRegAliveInBlock(VRInfo, BB);
HandlePhysRegDef(i, 0);
}
- BBMap.clear();
-
// Convert the information we have gathered into VirtRegInfo and transform it
// into a form usable by RegistersKilled.
//
projects / oota-llvm.git / blobdiff