LegalizeTypes soft-float support for stores of a

[oota-llvm.git] / lib / CodeGen / LiveVariables.cpp

diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index bc73b6841c4db9584ec99765a6fdacd725e8090f..82016ed591246dcaf4134baa79714f0d864375bd 100644 (file)
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -34,6 +34,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Config/alloca.h"
 #include <algorithm>
@@ -387,7 +388,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg) {
 
 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
   // What parts of the register are previously defined?
-  std::set<unsigned> Live;
+  SmallSet<unsigned, 32> Live;
   if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
     Live.insert(Reg);
     for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
@@ -602,7 +603,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
            I = MF->getRegInfo().liveout_begin(),
            E = MF->getRegInfo().liveout_end(); I != E; ++I) {
         assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
-               "Cannot have a live-in virtual register!");
+               "Cannot have a live-out virtual register!");
         HandlePhysRegUse(*I, Ret);
 
         // Add live-out registers as implicit uses.
@@ -652,35 +653,12 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
   return false;
 }
 
-/// instructionChanged - When the address of an instruction changes, this method
-/// should be called so that live variables can update its internal data
-/// structures.  This removes the records for OldMI, transfering them to the
-/// records for NewMI.
-void LiveVariables::instructionChanged(MachineInstr *OldMI,
-                                       MachineInstr *NewMI) {
-  // If the instruction defines any virtual registers, update the VarInfo,
-  // kill and dead information for the instruction.
-  for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = OldMI->getOperand(i);
-    if (MO.isRegister() && MO.getReg() &&
-        TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
-      unsigned Reg = MO.getReg();
-      VarInfo &VI = getVarInfo(Reg);
-      if (MO.isDef()) {
-        if (MO.isDead()) {
-          MO.setIsDead(false);
-          addVirtualRegisterDead(Reg, NewMI);
-        }
-      }
-      if (MO.isKill()) {
-        MO.setIsKill(false);
-        addVirtualRegisterKilled(Reg, NewMI);
-      }
-      // If this is a kill of the value, update the VI kills list.
-      if (VI.removeKill(OldMI))
-        VI.Kills.push_back(NewMI);   // Yes, there was a kill of it
-    }
-  }
+/// replaceKillInstruction - Update register kill info by replacing a kill
+/// instruction with a new one.
+void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
+                                           MachineInstr *NewMI) {
+  VarInfo &VI = getVarInfo(Reg);
+  std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
 }
 
 /// removeVirtualRegistersKilled - Remove all killed info for the specified
@@ -699,22 +677,6 @@ void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
   }
 }
 
-/// removeVirtualRegistersDead - Remove all of the dead registers for the
-/// specified instruction from the live variable information.
-void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
-  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI->getOperand(i);
-    if (MO.isRegister() && MO.isDead()) {
-      MO.setIsDead(false);
-      unsigned Reg = MO.getReg();
-      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-        bool removed = getVarInfo(Reg).removeKill(MI);
-        assert(removed && "kill not in register's VarInfo?");
-      }
-    }
-  }
-}
-
 /// analyzePHINodes - Gather information about the PHI nodes in here. In
 /// particular, we want to map the variable information of a virtual register
 /// which is used in a PHI node. We map that to the BB the vreg is coming from.