#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Config/alloca.h"
+#include <algorithm>
using namespace llvm;
-static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
+static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
+
+void LiveVariables::VarInfo::dump() const {
+ cerr << "Register Defined by: ";
+ if (DefInst)
+ cerr << *DefInst;
+ else
+ cerr << "<null>\n";
+ cerr << " Alive in blocks: ";
+ for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
+ if (AliveBlocks[i]) cerr << i << ", ";
+ cerr << " Used in blocks: ";
+ for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
+ if (UsedBlocks[i]) cerr << i << ", ";
+ cerr << "\n Killed by:";
+ if (Kills.empty())
+ cerr << " No instructions.\n";
+ else {
+ for (unsigned i = 0, e = Kills.size(); i != e; ++i)
+ cerr << "\n #" << i << ": " << *Kills[i];
+ cerr << "\n";
+ }
+}
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
else
VirtRegInfo.resize(2*VirtRegInfo.size());
}
- return VirtRegInfo[RegIdx];
+ VarInfo &VI = VirtRegInfo[RegIdx];
+ VI.AliveBlocks.resize(MF->getNumBlockIDs());
+ VI.UsedBlocks.resize(MF->getNumBlockIDs());
+ return VI;
+}
+
+bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isKill()) {
+ if (RegInfo->regsOverlap(Reg, MO.getReg()))
+ return true;
+ }
+ }
+ return false;
}
+bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDead())
+ if (RegInfo->regsOverlap(Reg, MO.getReg()))
+ return true;
+ }
+ return false;
+}
+bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDef()) {
+ if (RegInfo->regsOverlap(Reg, MO.getReg()))
+ return true;
+ }
+ }
+ return false;
+}
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
MachineBasicBlock *MBB) {
if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
- if (VRInfo.AliveBlocks.size() <= BBNum)
- VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
-
if (VRInfo.AliveBlocks[BBNum])
return; // We already know the block is live
MachineInstr *MI) {
assert(VRInfo.DefInst && "Register use before def!");
+ unsigned BBNum = MBB->getNumber();
+
+ VRInfo.UsedBlocks[BBNum] = true;
+
// Check to see if this basic block is already a kill block...
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the
"Should have kill for defblock!");
// Add a new kill entry for this basic block.
- VRInfo.Kills.push_back(MI);
+ // If this virtual register is already marked as alive in this basic block,
+ // that means it is alive in at least one of the successor block, it's not
+ // a kill.
+ if (!VRInfo.AliveBlocks[BBNum])
+ VRInfo.Kills.push_back(MI);
// Update all dominating blocks to mark them known live.
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
MarkVirtRegAliveInBlock(VRInfo, *PI);
}
+void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
+ MO.setIsKill();
+ break;
+ }
+ }
+}
+
+void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
+ MO.setIsDead();
+ break;
+ }
+ }
+}
+
void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
// Does this kill a previous version of this register?
if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
if (PhysRegUsed[Reg])
- RegistersKilled.insert(std::make_pair(LastUse, Reg));
+ addRegisterKilled(Reg, LastUse);
else
- RegistersDead.insert(std::make_pair(LastUse, Reg));
+ addRegisterDead(Reg, LastUse);
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
unsigned Alias = *AliasSet; ++AliasSet) {
if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
if (PhysRegUsed[Alias])
- RegistersKilled.insert(std::make_pair(LastUse, Alias));
+ addRegisterKilled(Alias, LastUse);
else
- RegistersDead.insert(std::make_pair(LastUse, Alias));
+ addRegisterDead(Alias, LastUse);
}
PhysRegInfo[Alias] = MI;
PhysRegUsed[Alias] = false;
}
}
-bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
- RegInfo = MF.getTarget().getRegisterInfo();
+bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
+ MF = &mf;
+ const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+ RegInfo = MF->getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
- AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
+ ReservedRegisters = RegInfo->getReservedRegs(mf);
// PhysRegInfo - Keep track of which instruction was the last use of a
// physical register. This is a purely local property, because all physical
/// Get some space for a respectable number of registers...
VirtRegInfo.resize(64);
- // Mark live-in registers as live-in.
- for (MachineFunction::livein_iterator I = MF.livein_begin(),
- E = MF.livein_end(); I != E; ++I) {
- assert(MRegisterInfo::isPhysicalRegister(I->first) &&
- "Cannot have a live-in virtual register!");
- HandlePhysRegDef(I->first, 0);
- }
+ analyzePHINodes(mf);
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
// nodes, which are treated as a special case).
//
- MachineBasicBlock *Entry = MF.begin();
+ MachineBasicBlock *Entry = MF->begin();
std::set<MachineBasicBlock*> Visited;
for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
MachineBasicBlock *MBB = *DFI;
- unsigned BBNum = MBB->getNumber();
+
+ // Mark live-in registers as live-in.
+ for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
+ EE = MBB->livein_end(); II != EE; ++II) {
+ assert(MRegisterInfo::isPhysicalRegister(*II) &&
+ "Cannot have a live-in virtual register!");
+ HandlePhysRegDef(*II, 0);
+ }
// Loop over all of the instructions, processing them.
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
MachineInstr *MI = I;
- const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI->getNumOperands();
if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
- // Loop over implicit uses, using them.
- for (const unsigned *ImplicitUses = MID.ImplicitUses;
- *ImplicitUses; ++ImplicitUses)
- HandlePhysRegUse(*ImplicitUses, MI);
-
- // Process all explicit uses...
+ // Process all uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isUse() && MO.isRegister() && MO.getReg()) {
+ if (MO.isRegister() && MO.isUse() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- AllocatablePhysicalRegisters[MO.getReg()]) {
+ !ReservedRegisters[MO.getReg()]) {
HandlePhysRegUse(MO.getReg(), MI);
}
}
}
- // Loop over implicit defs, defining them.
- for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
- *ImplicitDefs; ++ImplicitDefs)
- HandlePhysRegDef(*ImplicitDefs, MI);
-
- // Process all explicit defs...
+ // Process all defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.isDef() && MO.isRegister() && MO.getReg()) {
+ if (MO.isRegister() && MO.isDef() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
// Defaults to dead
VRInfo.Kills.push_back(MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- AllocatablePhysicalRegisters[MO.getReg()]) {
+ !ReservedRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
}
}
// bottom of this basic block. We check all of our successor blocks to see
// if they have PHI nodes, and if so, we simulate an assignment at the end
// of the current block.
- for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
- E = MBB->succ_end(); SI != E; ++SI) {
- MachineBasicBlock *Succ = *SI;
-
- // PHI nodes are guaranteed to be at the top of the block...
- for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
- MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
- for (unsigned i = 1; ; i += 2) {
- assert(MI->getNumOperands() > i+1 &&
- "Didn't find an entry for our predecessor??");
- if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.getVRegValueOrNull()) {
- VarInfo &VRInfo = getVarInfo(MO.getReg());
-
- // Only mark it alive only in the block we are representing...
- MarkVirtRegAliveInBlock(VRInfo, MBB);
- break; // Found the PHI entry for this block...
- }
- }
- }
+ if (!PHIVarInfo[MBB].empty()) {
+ std::vector<unsigned>& VarInfoVec = PHIVarInfo[MBB];
+
+ for (std::vector<unsigned>::iterator I = VarInfoVec.begin(),
+ E = VarInfoVec.end(); I != E; ++I) {
+ VarInfo& VRInfo = getVarInfo(*I);
+ assert(VRInfo.DefInst && "Register use before def (or no def)!");
+
+ // Only mark it alive only in the block we are representing.
+ MarkVirtRegAliveInBlock(VRInfo, MBB);
}
}
- // Finally, if the last block in the function is a return, make sure to mark
+ // Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
MachineInstr *Ret = &MBB->back();
- for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
- E = MF.liveout_end(); I != E; ++I) {
+ for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
+ E = MF->liveout_end(); I != E; ++I) {
assert(MRegisterInfo::isPhysicalRegister(*I) &&
"Cannot have a live-in virtual register!");
HandlePhysRegUse(*I, Ret);
+ // Add live-out registers as implicit uses.
+ Ret->addRegOperand(*I, false, true);
}
}
HandlePhysRegDef(i, 0);
}
- // Convert the information we have gathered into VirtRegInfo and transform it
- // into a form usable by RegistersKilled.
+ // Convert and transfer the dead / killed information we have gathered into
+ // VirtRegInfo onto MI's.
//
- for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
- for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
+ for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
+ for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
- RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j],
- i + MRegisterInfo::FirstVirtualRegister));
-
+ addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
+ VirtRegInfo[i].Kills[j]);
else
- RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j],
- i + MRegisterInfo::FirstVirtualRegister));
+ addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
+ VirtRegInfo[i].Kills[j]);
}
// Check to make sure there are no unreachable blocks in the MC CFG for the
// function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens.
#ifndef NDEBUG
- for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif
+ PHIVarInfo.clear();
return false;
}
/// the records for NewMI.
void LiveVariables::instructionChanged(MachineInstr *OldMI,
MachineInstr *NewMI) {
- // If the instruction defines any virtual registers, update the VarInfo for
- // the instruction.
+ // If the instruction defines any virtual registers, update the VarInfo,
+ // kill and dead information for the instruction.
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OldMI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);
if (MO.isDef()) {
+ if (MO.isDead()) {
+ MO.unsetIsDead();
+ addVirtualRegisterDead(Reg, NewMI);
+ }
// Update the defining instruction.
if (VI.DefInst == OldMI)
VI.DefInst = NewMI;
}
if (MO.isUse()) {
+ if (MO.isKill()) {
+ MO.unsetIsKill();
+ addVirtualRegisterKilled(Reg, NewMI);
+ }
// If this is a kill of the value, update the VI kills list.
if (VI.removeKill(OldMI))
VI.Kills.push_back(NewMI); // Yes, there was a kill of it
}
}
}
+}
+
+/// removeVirtualRegistersKilled - Remove all killed info for the specified
+/// instruction.
+void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isKill()) {
+ MO.unsetIsKill();
+ unsigned Reg = MO.getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg)) {
+ bool removed = getVarInfo(Reg).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ }
+ }
+}
+
+/// removeVirtualRegistersDead - Remove all of the dead registers for the
+/// specified instruction from the live variable information.
+void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDead()) {
+ MO.unsetIsDead();
+ unsigned Reg = MO.getReg();
+ if (MRegisterInfo::isVirtualRegister(Reg)) {
+ bool removed = getVarInfo(Reg).removeKill(MI);
+ assert(removed && "kill not in register's VarInfo?");
+ }
+ }
+ }
+}
- // Move the killed information over...
- killed_iterator I, E;
- tie(I, E) = killed_range(OldMI);
- std::vector<unsigned> Regs;
- for (killed_iterator A = I; A != E; ++A)
- Regs.push_back(A->second);
- RegistersKilled.erase(I, E);
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i)
- RegistersKilled.insert(std::make_pair(NewMI, Regs[i]));
- Regs.clear();
-
- // Move the dead information over...
- tie(I, E) = dead_range(OldMI);
- for (killed_iterator A = I; A != E; ++A)
- Regs.push_back(A->second);
- RegistersDead.erase(I, E);
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i)
- RegistersDead.insert(std::make_pair(NewMI, Regs[i]));
+/// analyzePHINodes - Gather information about the PHI nodes in here. In
+/// particular, we want to map the variable information of a virtual
+/// register which is used in a PHI node. We map that to the BB the vreg is
+/// coming from.
+///
+void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
+ for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
+ I != E; ++I)
+ for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
+ BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
+ for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
+ PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()].
+ push_back(BBI->getOperand(i).getReg());
}
projects / oota-llvm.git / blobdiff