//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the LiveVariable analysis pass. For each machine
// instruction in the function, this pass calculates the set of registers that
// are immediately dead after the instruction (i.e., the instruction calculates
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "Support/DepthFirstIterator.h"
-#include "Support/STLExtras.h"
+#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/Config/alloca.h"
+#include <algorithm>
using namespace llvm;
static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
return VirtRegInfo[RegIdx];
}
+bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
+ std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
+ RegistersKilled.find(MI);
+ if (I == RegistersKilled.end()) return false;
+
+ // Do a binary search, as these lists can grow pretty big, particularly for
+ // call instructions on targets with lots of call-clobbered registers.
+ return std::binary_search(I->second.begin(), I->second.end(), Reg);
+}
+
+bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
+ std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
+ RegistersDead.find(MI);
+ if (I == RegistersDead.end()) return false;
+
+ // Do a binary search, as these lists can grow pretty big, particularly for
+ // call instructions on targets with lots of call-clobbered registers.
+ return std::binary_search(I->second.begin(), I->second.end(), Reg);
+}
void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
// Check to see if this basic block is one of the killing blocks. If so,
// remove it...
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- if (VRInfo.Kills[i].first == MBB) {
+ if (VRInfo.Kills[i]->getParent() == MBB) {
VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
break;
}
- if (MBB == VRInfo.DefBlock) return; // Terminate recursion
+ if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
if (VRInfo.AliveBlocks.size() <= BBNum)
VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
MachineInstr *MI) {
+ assert(VRInfo.DefInst && "Register use before def!");
+
// Check to see if this basic block is already a kill block...
- if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
+ if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the
// live range by updating the kill instruction.
- VRInfo.Kills.back().second = MI;
+ VRInfo.Kills.back() = MI;
return;
}
#ifndef NDEBUG
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
- assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
+ assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
+ assert(MBB != VRInfo.DefInst->getParent() &&
+ "Should have kill for defblock!");
// Add a new kill entry for this basic block.
- VRInfo.Kills.push_back(std::make_pair(MBB, MI));
+ VRInfo.Kills.push_back(MI);
// Update all dominating blocks to mark them known live.
- const BasicBlock *BB = MBB->getBasicBlock();
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
E = MBB->pred_end(); PI != E; ++PI)
MarkVirtRegAliveInBlock(VRInfo, *PI);
// Does this kill a previous version of this register?
if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
if (PhysRegUsed[Reg])
- RegistersKilled.insert(std::make_pair(LastUse, Reg));
+ RegistersKilled[LastUse].push_back(Reg);
else
- RegistersDead.insert(std::make_pair(LastUse, Reg));
+ RegistersDead[LastUse].push_back(Reg);
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
unsigned Alias = *AliasSet; ++AliasSet) {
if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
if (PhysRegUsed[Alias])
- RegistersKilled.insert(std::make_pair(LastUse, Alias));
+ RegistersKilled[LastUse].push_back(Alias);
else
- RegistersDead.insert(std::make_pair(LastUse, Alias));
+ RegistersDead[LastUse].push_back(Alias);
}
PhysRegInfo[Alias] = MI;
PhysRegUsed[Alias] = false;
RegInfo = MF.getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
- // First time though, initialize AllocatablePhysicalRegisters for the target
- if (AllocatablePhysicalRegisters.empty()) {
- // Make space, initializing to false...
- AllocatablePhysicalRegisters.resize(RegInfo->getNumRegs());
-
- // Loop over all of the register classes...
- for (MRegisterInfo::regclass_iterator RCI = RegInfo->regclass_begin(),
- E = RegInfo->regclass_end(); RCI != E; ++RCI)
- // Loop over all of the allocatable registers in the function...
- for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
- E = (*RCI)->allocation_order_end(MF); I != E; ++I)
- AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
- }
+ AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
// PhysRegInfo - Keep track of which instruction was the last use of a
// physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks.
//
- MachineInstr *PhysRegInfoA[RegInfo->getNumRegs()];
- bool PhysRegUsedA[RegInfo->getNumRegs()];
- std::fill(PhysRegInfoA, PhysRegInfoA+RegInfo->getNumRegs(), (MachineInstr*)0);
- PhysRegInfo = PhysRegInfoA;
- PhysRegUsed = PhysRegUsedA;
+ PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
+ RegInfo->getNumRegs());
+ PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
+ std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
/// Get some space for a respectable number of registers...
VirtRegInfo.resize(64);
-
+
+ // Mark live-in registers as live-in.
+ for (MachineFunction::livein_iterator I = MF.livein_begin(),
+ E = MF.livein_end(); I != E; ++I) {
+ assert(MRegisterInfo::isPhysicalRegister(I->first) &&
+ "Cannot have a live-in virtual register!");
+ HandlePhysRegDef(I->first, 0);
+ }
+
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks.
- if (MI->getOpcode() == TargetInstrInfo::PHI)
+ if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
- assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
- VRInfo.DefBlock = MBB; // Created here...
+ assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
VRInfo.DefInst = MI;
- VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
+ // Defaults to dead
+ VRInfo.Kills.push_back(MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
AllocatablePhysicalRegisters[MO.getReg()]) {
HandlePhysRegDef(MO.getReg(), MI);
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
E = MBB->succ_end(); SI != E; ++SI) {
MachineBasicBlock *Succ = *SI;
-
+
// PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
}
}
}
-
+
+ // Finally, if the last block in the function is a return, make sure to mark
+ // it as using all of the live-out values in the function.
+ if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
+ MachineInstr *Ret = &MBB->back();
+ for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
+ E = MF.liveout_end(); I != E; ++I) {
+ assert(MRegisterInfo::isPhysicalRegister(*I) &&
+ "Cannot have a live-in virtual register!");
+ HandlePhysRegUse(*I, Ret);
+ }
+ }
+
// Loop over PhysRegInfo, killing any registers that are available at the
// end of the basic block. This also resets the PhysRegInfo map.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
//
for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
- if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
- RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
- i + MRegisterInfo::FirstVirtualRegister));
+ if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
+ RegistersDead[VirtRegInfo[i].Kills[j]].push_back(
+ i + MRegisterInfo::FirstVirtualRegister);
else
- RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
- i + MRegisterInfo::FirstVirtualRegister));
+ RegistersKilled[VirtRegInfo[i].Kills[j]].push_back(
+ i + MRegisterInfo::FirstVirtualRegister);
}
+ // Walk through the RegistersKilled/Dead sets, and sort the registers killed
+ // or dead. This allows us to use efficient binary search for membership
+ // testing.
+ for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
+ I = RegistersKilled.begin(), E = RegistersKilled.end(); I != E; ++I)
+ std::sort(I->second.begin(), I->second.end());
+ for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
+ I = RegistersDead.begin(), E = RegistersDead.end(); I != E; ++I)
+ std::sort(I->second.begin(), I->second.end());
+
+ // Check to make sure there are no unreachable blocks in the MC CFG for the
+ // function. If so, it is due to a bug in the instruction selector or some
+ // other part of the code generator if this happens.
+#ifndef NDEBUG
+ for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ assert(Visited.count(&*i) != 0 && "unreachable basic block found");
+#endif
+
return false;
}
// the instruction.
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = OldMI->getOperand(i);
- if (MO.isRegister() && MO.isDef() && MO.getReg() &&
+ if (MO.isRegister() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);
- if (VI.DefInst == OldMI)
- VI.DefInst = NewMI;
+ if (MO.isDef()) {
+ // Update the defining instruction.
+ if (VI.DefInst == OldMI)
+ VI.DefInst = NewMI;
+ }
+ if (MO.isUse()) {
+ // If this is a kill of the value, update the VI kills list.
+ if (VI.removeKill(OldMI))
+ VI.Kills.push_back(NewMI); // Yes, there was a kill of it
+ }
}
}
// Move the killed information over...
killed_iterator I, E;
tie(I, E) = killed_range(OldMI);
- std::vector<unsigned> Regs;
- for (killed_iterator A = I; A != E; ++A)
- Regs.push_back(A->second);
- RegistersKilled.erase(I, E);
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i)
- RegistersKilled.insert(std::make_pair(NewMI, Regs[i]));
- Regs.clear();
+ if (I != E) {
+ std::vector<unsigned> &V = RegistersKilled[NewMI];
+ bool WasEmpty = V.empty();
+ V.insert(V.end(), I, E);
+ if (!WasEmpty)
+ std::sort(V.begin(), V.end()); // Keep the reg list sorted.
+ RegistersKilled.erase(OldMI);
+ }
// Move the dead information over...
tie(I, E) = dead_range(OldMI);
- for (killed_iterator A = I; A != E; ++A)
- Regs.push_back(A->second);
- RegistersDead.erase(I, E);
-
- for (unsigned i = 0, e = Regs.size(); i != e; ++i)
- RegistersDead.insert(std::make_pair(NewMI, Regs[i]));
+ if (I != E) {
+ std::vector<unsigned> &V = RegistersDead[NewMI];
+ bool WasEmpty = V.empty();
+ V.insert(V.end(), I, E);
+ if (!WasEmpty)
+ std::sort(V.begin(), V.end()); // Keep the reg list sorted.
+ RegistersDead.erase(OldMI);
+ }
}
projects / oota-llvm.git / blobdiff