add scaffolding for splitting of vectors.

[oota-llvm.git] / lib / CodeGen / LowerSubregs.cpp

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 830384427dea52e2a568c6124ef599e11c3a78b2..1b7f70e05ab31fa564211ce6b16e580516eec679 100644 (file)
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -59,17 +59,6 @@ static const TargetRegisterClass *getPhysicalRegisterRegClass(
   return 0;
 }
 
-static bool isSubRegOf(const MRegisterInfo &MRI,
-                       unsigned SubReg,
-                       unsigned SupReg) {
-  const TargetRegisterDesc &RD = MRI[SubReg];
-  for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
-    if (*reg == SupReg)
-      return true;
-      
-  return false;
-}
-
 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    MachineBasicBlock *MBB = MI->getParent();
    MachineFunction &MF = *MBB->getParent();
@@ -77,7 +66,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    
    assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
           MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
-          MI->getOperand(2).isImm() && "Malformed extract_subreg");
+          MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
 
    unsigned SuperReg = MI->getOperand(1).getReg();
    unsigned SubIdx = MI->getOperand(2).getImm();
@@ -99,13 +88,13 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
      assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
              "Extract subreg and Dst must be of same register class");
 
-     MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC);
+     MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
      MachineBasicBlock::iterator dMI = MI;
      DOUT << "subreg: " << *(--dMI);
    }
 
    DOUT << "\n";
-   MBB->erase(MI);
+   MBB->remove(MI);
    return true;
 }
 
@@ -124,7 +113,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   if (MI->getNumOperands() == 3) {
     assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
            (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-            MI->getOperand(2).isImm() && "Invalid extract_subreg");
+            MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
     DstReg = MI->getOperand(0).getReg();
     SrcReg = DstReg;
     InsReg = MI->getOperand(1).getReg();
@@ -133,7 +122,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
            (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
            (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
-            MI->getOperand(3).isImm() && "Invalid extract_subreg");
+            MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
     DstReg = MI->getOperand(0).getReg();
     SrcReg = MI->getOperand(1).getReg();
     InsReg = MI->getOperand(2).getReg();
@@ -157,8 +146,8 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   // of the destination, we copy the subreg into the source
   // However, this is only safe if the insert instruction is the kill
   // of the source register
-  bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);    
-  if (revCopyOrder) {
+  bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg);
+  if (revCopyOrder && InsReg != DstSubReg) {
     if (MI->getOperand(1).isKill()) {
       DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
       // Insert sub-register copy
@@ -168,14 +157,21 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
       } else {
         TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
       }
-    
-      MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+      MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+
+#ifndef NDEBUG
       MachineBasicBlock::iterator dMI = MI;
       DOUT << "subreg: " << *(--dMI);
+#endif
     } else {
       assert(0 && "Don't know how to convert this insert");
     }
   }
+#ifndef NDEBUG
+  if (InsReg == DstSubReg) {
+     DOUT << "subreg: Eliminated subreg copy\n";
+  }
+#endif
 
   if (SrcReg != DstReg) {
     // Insert super-register copy
@@ -188,10 +184,19 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
             "Insert superreg and Dst must be of same register class");
 
-    MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
+    MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+
+#ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
     DOUT << "subreg: " << *(--dMI);
+#endif
+  }
+  
+#ifndef NDEBUG
+  if (SrcReg == DstReg) {
+     DOUT << "subreg: Eliminated superreg copy\n";
   }
+#endif
 
   if (!revCopyOrder && InsReg != DstSubReg) {
     // Insert sub-register copy
@@ -201,14 +206,16 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     } else {
       TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
     }
-  
-    MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
+    MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+
+#ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
     DOUT << "subreg: " << *(--dMI);
+#endif
   }
 
   DOUT << "\n";
-  MBB->erase(MI);
+  MBB->remove(MI);
   return true;                    
 }