//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Christopher Lamb and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a MachineFunction pass which runs after register
+// allocation that turns subreg insert/extract instructions into register
+// copies, as needed. This ensures correct codegen even if the coalescer
+// isn't able to remove all subreg instructions.
//
//===----------------------------------------------------------------------===//
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Compiler.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
- struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
- : public MachineFunctionPass {
+ struct LowerSubregsInstructionPass : public MachineFunctionPass {
+ private:
+ const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII;
+
+ public:
static char ID; // Pass identification, replacement for typeid
- LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
-
+ LowerSubregsInstructionPass() : MachineFunctionPass(ID) {}
+
const char *getPassName() const {
return "Subregister lowering instruction pass";
}
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
/// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&);
+
+ private:
+ bool LowerSubregToReg(MachineInstr *MI);
+ bool LowerCopy(MachineInstr *MI);
+
+ void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
+ const TargetRegisterInfo *TRI);
+ void TransferImplicitDefs(MachineInstr *MI);
};
char LowerSubregsInstructionPass::ID = 0;
}
-FunctionPass *llvm::createLowerSubregsPass() {
- return new LowerSubregsInstructionPass();
+FunctionPass *llvm::createLowerSubregsPass() {
+ return new LowerSubregsInstructionPass();
+}
+
+/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
+/// and the lowered replacement instructions immediately precede it.
+/// Mark the replacement instructions with the dead flag.
+void
+LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
+ unsigned DstReg,
+ const TargetRegisterInfo *TRI) {
+ for (MachineBasicBlock::iterator MII =
+ prior(MachineBasicBlock::iterator(MI)); ; --MII) {
+ if (MII->addRegisterDead(DstReg, TRI))
+ break;
+ assert(MII != MI->getParent()->begin() &&
+ "copyPhysReg output doesn't reference destination register!");
+ }
}
-// Returns the Register Class of a physical register
-static const TargetRegisterClass *getPhysicalRegisterRegClass(
- const MRegisterInfo &MRI,
- unsigned reg) {
- assert(MRegisterInfo::isPhysicalRegister(reg) &&
- "reg must be a physical register");
- // Pick the register class of the right type that contains this physreg.
- for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
- E = MRI.regclass_end(); I != E; ++I)
- if ((*I)->contains(reg))
- return *I;
- assert(false && "Couldn't find the register class");
- return 0;
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it. Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+ MachineBasicBlock::iterator CopyMI = MI;
+ --CopyMI;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+ continue;
+ CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+ }
}
-static bool isSubRegOf(const MRegisterInfo &MRI,
- unsigned SubReg,
- unsigned SupReg) {
- const TargetRegisterDesc &RD = MRI[SubReg];
- for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
- if (*reg == SupReg)
+bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
+ MachineBasicBlock *MBB = MI->getParent();
+ assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
+ MI->getOperand(1).isImm() &&
+ (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
+ MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
+
+ unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned InsReg = MI->getOperand(2).getReg();
+ assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
+ unsigned SubIdx = MI->getOperand(3).getImm();
+
+ assert(SubIdx != 0 && "Invalid index for insert_subreg");
+ unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
+
+ assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
+ "Insert destination must be in a physical register");
+ assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
+ "Inserted value must be in a physical register");
+
+ DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
+
+ if (DstSubReg == InsReg) {
+ // No need to insert an identify copy instruction.
+ // Watch out for case like this:
+ // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
+ // We must leave %RAX live.
+ if (DstReg != InsReg) {
+ MI->setDesc(TII->get(TargetOpcode::KILL));
+ MI->RemoveOperand(3); // SubIdx
+ MI->RemoveOperand(1); // Imm
+ DEBUG(dbgs() << "subreg: replace by: " << *MI);
return true;
-
- return false;
+ }
+ DEBUG(dbgs() << "subreg: eliminated!");
+ } else {
+ TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
+ MI->getOperand(2).isKill());
+ // Transfer the kill/dead flags, if needed.
+ if (MI->getOperand(0).isDead())
+ TransferDeadFlag(MI, DstSubReg, TRI);
+ DEBUG({
+ MachineBasicBlock::iterator dMI = MI;
+ dbgs() << "subreg: " << *(--dMI);
+ });
+ }
+
+ DEBUG(dbgs() << '\n');
+ MBB->erase(MI);
+ return true;
}
+bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+ MachineOperand &DstMO = MI->getOperand(0);
+ MachineOperand &SrcMO = MI->getOperand(1);
+
+ if (SrcMO.getReg() == DstMO.getReg()) {
+ DEBUG(dbgs() << "identity copy: " << *MI);
+ // No need to insert an identity copy instruction, but replace with a KILL
+ // if liveness is changed.
+ if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
+ // We must make sure the super-register gets killed. Replace the
+ // instruction with KILL.
+ MI->setDesc(TII->get(TargetOpcode::KILL));
+ DEBUG(dbgs() << "replaced by: " << *MI);
+ return true;
+ }
+ // Vanilla identity copy.
+ MI->eraseFromParent();
+ return true;
+ }
+
+ DEBUG(dbgs() << "real copy: " << *MI);
+ TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
+ DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
+
+ if (DstMO.isDead())
+ TransferDeadFlag(MI, DstMO.getReg(), TRI);
+ if (MI->getNumOperands() > 2)
+ TransferImplicitDefs(MI);
+ DEBUG({
+ MachineBasicBlock::iterator dMI = MI;
+ dbgs() << "replaced by: " << *(--dMI);
+ });
+ MI->eraseFromParent();
+ return true;
+}
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
/// copies.
///
bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
- DOUT << "Machine Function\n";
- const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
-
- bool MadeChange = false;
+ DEBUG(dbgs() << "Machine Function\n"
+ << "********** LOWERING SUBREG INSTRS **********\n"
+ << "********** Function: "
+ << MF.getFunction()->getName() << '\n');
+ TRI = MF.getTarget().getRegisterInfo();
+ TII = MF.getTarget().getInstrInfo();
- DOUT << "********** LOWERING SUBREG INSTRS **********\n";
- DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
+ bool MadeChange = false;
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
- mi != me; ++mi) {
-
- if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
- assert(mi->getOperand(0).isRegister() && mi->getOperand(0).isDef() &&
- mi->getOperand(1).isRegister() && mi->getOperand(1).isUse() &&
- mi->getOperand(2).isImm() && "Malformed extract_subreg");
-
- unsigned SuperReg = mi->getOperand(1).getReg();
- unsigned SubIdx = mi->getOperand(2).getImm();
-
- assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
- "Extract supperg source must be a physical register");
- unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
- unsigned DstReg = mi->getOperand(0).getReg();
-
- DOUT << "subreg: CONVERTING: " << *mi;
-
- if (SrcReg != DstReg) {
- const TargetRegisterClass *TRC = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC = getPhysicalRegisterRegClass(MRI, DstReg);
- } else {
- TRC = MF.getSSARegMap()->getRegClass(DstReg);
- }
- assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
- "Extract subreg and Dst must be of same register class");
-
- MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC);
- MachineBasicBlock::iterator dmi = mi;
- DOUT << "subreg: " << *(--dmi);
- }
-
- DOUT << "\n";
- mbbi->erase(mi);
- MadeChange = true;
-
- } else if (mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
-
- unsigned DstReg = 0;
- unsigned SrcReg = 0;
- unsigned InsReg = 0;
- unsigned SubIdx = 0;
-
- // If only have 3 operands, then the source superreg is undef
- // and we can supress the copy from the undef value
- if (mi->getNumOperands() == 3) {
- assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
- (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
- mi->getOperand(2).isImm() && "Invalid extract_subreg");
- DstReg = mi->getOperand(0).getReg();
- SrcReg = DstReg;
- InsReg = mi->getOperand(1).getReg();
- SubIdx = mi->getOperand(2).getImm();
- } else if (mi->getNumOperands() == 4) {
- assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
- (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
- (mi->getOperand(2).isRegister() && mi->getOperand(2).isUse()) &&
- mi->getOperand(3).isImm() && "Invalid extract_subreg");
- DstReg = mi->getOperand(0).getReg();
- SrcReg = mi->getOperand(1).getReg();
- InsReg = mi->getOperand(2).getReg();
- SubIdx = mi->getOperand(3).getImm();
- } else
- assert(0 && "Malformed extract_subreg");
-
- assert(SubIdx != 0 && "Invalid index for extract_subreg");
- unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
-
- assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
- "Insert superreg source must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
- "Insert destination must be in a physical register");
- assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
- "Inserted value must be in a physical register");
-
- DOUT << "subreg: CONVERTING: " << *mi;
-
- // If the inserted register is already allocated into a subregister
- // of the destination, we copy the subreg into the source
- // However, this is only safe if the insert instruction is the kill
- // of the source register
- bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
- if (revCopyOrder) {
- if (mi->getOperand(1).isKill()) {
- DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
- // Insert sub-register copy
- const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
- } else {
- TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
- }
-
- MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
- MachineBasicBlock::iterator dmi = mi;
- DOUT << "subreg: " << *(--dmi);
- } else {
- assert(0 && "Don't know how to convert this insert");
- }
- }
-
- if (SrcReg != DstReg) {
- // Insert super-register copy
- const TargetRegisterClass *TRC0 = 0;
- if (MRegisterInfo::isPhysicalRegister(DstReg)) {
- TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
- } else {
- TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
- }
- assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
- "Insert superreg and Dst must be of same register class");
-
- MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC0);
- MachineBasicBlock::iterator dmi = mi;
- DOUT << "subreg: " << *(--dmi);
- }
-
- if (!revCopyOrder && InsReg != DstSubReg) {
- // Insert sub-register copy
- const TargetRegisterClass *TRC1 = 0;
- if (MRegisterInfo::isPhysicalRegister(InsReg)) {
- TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
- } else {
- TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
- }
-
- MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
- MachineBasicBlock::iterator dmi = mi;
- DOUT << "subreg: " << *(--dmi);
- }
-
- DOUT << "\n";
- mbbi->erase(mi);
- MadeChange = true;
+ mi != me;) {
+ MachineBasicBlock::iterator nmi = llvm::next(mi);
+ MachineInstr *MI = mi;
+ assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
+ assert(MI->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
+ "EXTRACT_SUBREG should no longer appear");
+ if (MI->isSubregToReg()) {
+ MadeChange |= LowerSubregToReg(MI);
+ } else if (MI->isCopy()) {
+ MadeChange |= LowerCopy(MI);
}
+ mi = nmi;
}
}
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