#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesCFG();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo &TRI);
void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
- const TargetRegisterInfo &TRI);
+ const TargetRegisterInfo &TRI,
+ bool AddIfNotFound = false);
};
char LowerSubregsInstructionPass::ID = 0;
void
LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
unsigned SrcReg,
- const TargetRegisterInfo &TRI) {
+ const TargetRegisterInfo &TRI,
+ bool AddIfNotFound) {
for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
- if (MII->addRegisterKilled(SrcReg, &TRI))
+ if (MII->addRegisterKilled(SrcReg, &TRI, AddIfNotFound))
break;
assert(MII != MI->getParent()->begin() &&
"copyRegToReg output doesn't reference source register!");
MachineFunction &MF = *MBB->getParent();
const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-
+
assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
MI->getOperand(2).isImm() && "Malformed extract_subreg");
"Extract supperg source must be a physical register");
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Extract destination must be in a physical register");
-
+ assert(SrcReg && "invalid subregister index for register");
+
DOUT << "subreg: CONVERTING: " << *MI;
if (SrcReg == DstReg) {
- // No need to insert an identify copy instruction.
+ // No need to insert an identity copy instruction.
+ if (MI->getOperand(1).isKill()) {
+ // We must make sure the super-register gets killed.Replace the
+ // instruction with IMPLICIT_DEF.
+ MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
+ MI->RemoveOperand(2); // SubIdx
+ DOUT << "subreg: replace by: " << *MI;
+ return true;
+ }
DOUT << "subreg: eliminated!";
- // Find the kill of the destination register's live range, and insert
- // a kill of the source register at that point.
- if (MI->getOperand(1).isKill() && !MI->getOperand(0).isDead())
- for (MachineBasicBlock::iterator MII =
- next(MachineBasicBlock::iterator(MI));
- MII != MBB->end(); ++MII)
- if (MII->killsRegister(DstReg, &TRI)) {
- MII->addRegisterKilled(SuperReg, &TRI, /*AddIfNotFound=*/true);
- break;
- }
} else {
// Insert copy
const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstReg, TRI);
if (MI->getOperand(1).isKill())
- TransferKillFlag(MI, SrcReg, TRI);
+ TransferKillFlag(MI, SuperReg, TRI, true);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
assert(SubIdx != 0 && "Invalid index for insert_subreg");
unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
-
+ assert(DstSubReg && "invalid subregister index for register");
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register");
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
DOUT << "subreg: CONVERTING: " << *MI;
if (DstSubReg == InsReg) {
- // No need to insert an identify copy instruction.
- DOUT << "subreg: eliminated!";
+ // No need to insert an identity copy instruction. If the SrcReg was
+ // <undef>, we need to make sure it is alive by inserting an IMPLICIT_DEF
+ if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
+ MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
+ TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg);
+ if (MI->getOperand(2).isUndef())
+ MIB.addReg(InsReg, RegState::Implicit | RegState::Undef);
+ else
+ MIB.addReg(InsReg, RegState::ImplicitKill);
+ } else {
+ DOUT << "subreg: eliminated!\n";
+ MBB->erase(MI);
+ return true;
+ }
} else {
// Insert sub-register copy
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
- TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ if (MI->getOperand(2).isUndef())
+ // If the source register being inserted is undef, then this becomes an
+ // implicit_def.
+ BuildMI(*MBB, MI, MI->getDebugLoc(),
+ TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg);
+ else
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ MachineBasicBlock::iterator CopyMI = MI;
+ --CopyMI;
+
+ // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
+ if (!MI->getOperand(1).isUndef())
+ CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
+
// Transfer the kill/dead flags, if needed.
- if (MI->getOperand(0).isDead())
+ if (MI->getOperand(0).isDead()) {
TransferDeadFlag(MI, DstSubReg, TRI);
- if (MI->getOperand(1).isKill())
+ } else {
+ // Make sure the full DstReg is live after this replacement.
+ CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
+ }
+
+ // Make sure the inserted register gets killed
+ if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
TransferKillFlag(MI, InsReg, TRI);
+ }
#ifndef NDEBUG
- MachineBasicBlock::iterator dMI = MI;
- DOUT << "subreg: " << *(--dMI);
+ MachineBasicBlock::iterator dMI = MI;
+ DOUT << "subreg: " << *(--dMI);
#endif
- }
DOUT << "\n";
MBB->erase(MI);
- return true;
+ return true;
}
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
projects / oota-llvm.git / blobdiff