#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrDesc.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/LeakDetector.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Assembly/Writer.h"
#include <algorithm>
using namespace llvm;
MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
- : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false) {
+ : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false),
+ AddressTaken(false) {
Insts.Parent = this;
}
LeakDetector::removeGarbageObject(this);
}
-std::ostream& llvm::operator<<(std::ostream &OS, const MachineBasicBlock &MBB) {
- MBB.print(OS);
- return OS;
-}
-raw_ostream& llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
MBB.print(OS);
return OS;
}
/// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
/// gets the next available unique MBB number. If it is removed from a
/// MachineFunction, it goes back to being #-1.
-void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock* N) {
+void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
MachineFunction &MF = *N->getParent();
N->Number = MF.addToMBBNumbering(N);
LeakDetector::removeGarbageObject(N);
}
-void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock* N) {
+void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
N->getParent()->removeFromMBBNumbering(N->Number);
N->Number = -1;
LeakDetector::addGarbageObject(N);
/// addNodeToList (MI) - When we add an instruction to a basic block
/// list, we update its parent pointer and add its operands from reg use/def
/// lists if appropriate.
-void ilist_traits<MachineInstr>::addNodeToList(MachineInstr* N) {
+void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
assert(N->getParent() == 0 && "machine instruction already in a basic block");
N->setParent(Parent);
/// removeNodeFromList (MI) - When we remove an instruction from a basic block
/// list, we update its parent pointer and remove its operands from reg use/def
/// lists if appropriate.
-void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr* N) {
+void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
assert(N->getParent() != 0 && "machine instruction not in a basic block");
// Remove from the use/def lists.
/// transferNodesFromList (MI) - When moving a range of instructions from one
/// MBB list to another, we need to update the parent pointers and the use/def
/// lists.
-void ilist_traits<MachineInstr>::transferNodesFromList(
- ilist_traits<MachineInstr>& fromList,
- MachineBasicBlock::iterator first,
- MachineBasicBlock::iterator last) {
+void ilist_traits<MachineInstr>::
+transferNodesFromList(ilist_traits<MachineInstr> &fromList,
+ MachineBasicBlock::iterator first,
+ MachineBasicBlock::iterator last) {
assert(Parent->getParent() == fromList.Parent->getParent() &&
"MachineInstr parent mismatch!");
return I;
}
+/// isOnlyReachableViaFallthough - Return true if this basic block has
+/// exactly one predecessor and the control transfer mechanism between
+/// the predecessor and this block is a fall-through.
bool MachineBasicBlock::isOnlyReachableByFallthrough() const {
// If this is a landing pad, it isn't a fall through. If it has no preds,
// then nothing falls through to it.
// If there isn't exactly one predecessor, it can't be a fall through.
const_pred_iterator PI = pred_begin(), PI2 = PI;
- ++PI;
- if (PI != pred_end())
+ ++PI2;
+ if (PI2 != pred_end())
return false;
// The predecessor has to be immediately before this block.
// Otherwise, check the last instruction.
const MachineInstr &LastInst = Pred->back();
- return LastInst.getDesc().isBarrier();
+ return !LastInst.getDesc().isBarrier();
}
void MachineBasicBlock::dump() const {
- print(*cerr.stream());
+ print(errs());
}
static inline void OutputReg(raw_ostream &os, unsigned RegNo,
const TargetRegisterInfo *TRI = 0) {
- if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
+ if (RegNo != 0 && TargetRegisterInfo::isPhysicalRegister(RegNo)) {
if (TRI)
os << " %" << TRI->get(RegNo).Name;
else
- os << " %mreg(" << RegNo << ")";
+ os << " %physreg" << RegNo;
} else
os << " %reg" << RegNo;
}
-void MachineBasicBlock::print(std::ostream &OS,
- const PrefixPrinter &prefix) const {
- raw_os_ostream RawOS(OS);
- print(RawOS, prefix);
+StringRef MachineBasicBlock::getName() const {
+ if (const BasicBlock *LBB = getBasicBlock())
+ return LBB->getName();
+ else
+ return "(null)";
}
-void MachineBasicBlock::print(raw_ostream &OS,
- const PrefixPrinter &prefix) const {
+void MachineBasicBlock::print(raw_ostream &OS) const {
const MachineFunction *MF = getParent();
- if(!MF) {
+ if (!MF) {
OS << "Can't print out MachineBasicBlock because parent MachineFunction"
<< " is null\n";
return;
}
- const BasicBlock *LBB = getBasicBlock();
- OS << "\n";
- if (LBB) OS << LBB->getName() << ": ";
- OS << (const void*)this
- << ", LLVM BB @" << (const void*) LBB << ", ID#" << getNumber();
- if (Alignment) OS << ", Alignment " << Alignment;
- if (isLandingPad()) OS << ", EH LANDING PAD";
- OS << ":\n";
+ if (Alignment) { OS << "Alignment " << Alignment << "\n"; }
+
+ OS << "BB#" << getNumber() << ": ";
+
+ const char *Comma = "";
+ if (const BasicBlock *LBB = getBasicBlock()) {
+ OS << Comma << "derived from LLVM BB ";
+ WriteAsOperand(OS, LBB, /*PrintType=*/false);
+ Comma = ", ";
+ }
+ if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
+ if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
+ OS << '\n';
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
if (!livein_empty()) {
- OS << "Live Ins:";
+ OS << " Live Ins:";
for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
OutputReg(OS, *I, TRI);
- OS << "\n";
+ OS << '\n';
}
// Print the preds of this block according to the CFG.
if (!pred_empty()) {
OS << " Predecessors according to CFG:";
for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
- OS << " " << *PI << " (#" << (*PI)->getNumber() << ")";
- OS << "\n";
+ OS << " BB#" << (*PI)->getNumber();
+ OS << '\n';
}
for (const_iterator I = begin(); I != end(); ++I) {
- prefix(OS, *I) << "\t";
+ OS << '\t';
I->print(OS, &getParent()->getTarget());
}
if (!succ_empty()) {
OS << " Successors according to CFG:";
for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI)
- OS << " " << *SI << " (#" << (*SI)->getNumber() << ")";
- OS << "\n";
+ OS << " BB#" << (*SI)->getNumber();
+ OS << '\n';
}
}
getParent()->splice(++BBI, this);
}
+void MachineBasicBlock::updateTerminator() {
+ const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo();
+ // A block with no successors has no concerns with fall-through edges.
+ if (this->succ_empty()) return;
+
+ MachineBasicBlock *TBB = 0, *FBB = 0;
+ SmallVector<MachineOperand, 4> Cond;
+ bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
+ (void) B;
+ assert(!B && "UpdateTerminators requires analyzable predecessors!");
+ if (Cond.empty()) {
+ if (TBB) {
+ // The block has an unconditional branch. If its successor is now
+ // its layout successor, delete the branch.
+ if (isLayoutSuccessor(TBB))
+ TII->RemoveBranch(*this);
+ } else {
+ // The block has an unconditional fallthrough. If its successor is not
+ // its layout successor, insert a branch.
+ TBB = *succ_begin();
+ if (!isLayoutSuccessor(TBB))
+ TII->InsertBranch(*this, TBB, 0, Cond);
+ }
+ } else {
+ if (FBB) {
+ // The block has a non-fallthrough conditional branch. If one of its
+ // successors is its layout successor, rewrite it to a fallthrough
+ // conditional branch.
+ if (isLayoutSuccessor(TBB)) {
+ if (TII->ReverseBranchCondition(Cond))
+ return;
+ TII->RemoveBranch(*this);
+ TII->InsertBranch(*this, FBB, 0, Cond);
+ } else if (isLayoutSuccessor(FBB)) {
+ TII->RemoveBranch(*this);
+ TII->InsertBranch(*this, TBB, 0, Cond);
+ }
+ } else {
+ // The block has a fallthrough conditional branch.
+ MachineBasicBlock *MBBA = *succ_begin();
+ MachineBasicBlock *MBBB = *llvm::next(succ_begin());
+ if (MBBA == TBB) std::swap(MBBB, MBBA);
+ if (isLayoutSuccessor(TBB)) {
+ if (TII->ReverseBranchCondition(Cond)) {
+ // We can't reverse the condition, add an unconditional branch.
+ Cond.clear();
+ TII->InsertBranch(*this, MBBA, 0, Cond);
+ return;
+ }
+ TII->RemoveBranch(*this);
+ TII->InsertBranch(*this, MBBA, 0, Cond);
+ } else if (!isLayoutSuccessor(MBBA)) {
+ TII->RemoveBranch(*this);
+ TII->InsertBranch(*this, TBB, MBBA, Cond);
+ }
+ }
+ }
+}
void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ) {
Successors.push_back(succ);
Predecessors.erase(I);
}
-void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB)
-{
+void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
if (this == fromMBB)
return;
- for(MachineBasicBlock::succ_iterator iter = fromMBB->succ_begin(),
- end = fromMBB->succ_end(); iter != end; ++iter) {
- addSuccessor(*iter);
- }
- while(!fromMBB->succ_empty())
+ for (MachineBasicBlock::succ_iterator I = fromMBB->succ_begin(),
+ E = fromMBB->succ_end(); I != E; ++I)
+ addSuccessor(*I);
+
+ while (!fromMBB->succ_empty())
fromMBB->removeSuccessor(fromMBB->succ_begin());
}
bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
MachineFunction::const_iterator I(this);
- return next(I) == MachineFunction::const_iterator(MBB);
+ return llvm::next(I) == MachineFunction::const_iterator(MBB);
+}
+
+bool MachineBasicBlock::canFallThrough() {
+ MachineBasicBlock *TBB = 0, *FBB = 0;
+ SmallVector<MachineOperand, 4> Cond;
+ const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo();
+ bool BranchUnAnalyzable = TII->AnalyzeBranch(*this, TBB, FBB, Cond, true);
+
+ MachineFunction::iterator Fallthrough = this;
+ ++Fallthrough;
+ // If FallthroughBlock is off the end of the function, it can't fall through.
+ if (Fallthrough == getParent()->end())
+ return false;
+
+ // If FallthroughBlock isn't a successor, no fallthrough is possible.
+ if (!isSuccessor(Fallthrough))
+ return false;
+
+ // If we couldn't analyze the branch, examine the last instruction.
+ // If the block doesn't end in a known control barrier, assume fallthrough
+ // is possible. The isPredicable check is needed because this code can be
+ // called during IfConversion, where an instruction which is normally a
+ // Barrier is predicated and thus no longer an actual control barrier. This
+ // is over-conservative though, because if an instruction isn't actually
+ // predicated we could still treat it like a barrier.
+ if (BranchUnAnalyzable)
+ return empty() || !back().getDesc().isBarrier() ||
+ back().getDesc().isPredicable();
+
+ // If there is no branch, control always falls through.
+ if (TBB == 0) return true;
+
+ // If there is some explicit branch to the fallthrough block, it can obviously
+ // reach, even though the branch should get folded to fall through implicitly.
+ if (MachineFunction::iterator(TBB) == Fallthrough ||
+ MachineFunction::iterator(FBB) == Fallthrough)
+ return true;
+
+ // If it's an unconditional branch to some block not the fall through, it
+ // doesn't fall through.
+ if (Cond.empty()) return false;
+
+ // Otherwise, if it is conditional and has no explicit false block, it falls
+ // through.
+ return FBB == 0;
}
/// removeFromParent - This method unlinks 'this' from the containing function,
bool MadeChange = false;
bool AddedFallThrough = false;
- MachineFunction::iterator FallThru = next(MachineFunction::iterator(this));
+ MachineFunction::iterator FallThru =
+ llvm::next(MachineFunction::iterator(this));
// If this block ends with a conditional branch that falls through to its
// successor, set DestB as the successor.
MachineBasicBlock::succ_iterator SI = succ_begin();
MachineBasicBlock *OrigDestA = DestA, *OrigDestB = DestB;
while (SI != succ_end()) {
- if (*SI == DestA && DestA == DestB) {
- DestA = DestB = 0;
- ++SI;
- } else if (*SI == DestA) {
+ if (*SI == DestA) {
DestA = 0;
++SI;
} else if (*SI == DestB) {
}
return MadeChange;
}
+
+void llvm::WriteAsOperand(raw_ostream &OS, const MachineBasicBlock *MBB,
+ bool t) {
+ OS << "BB#" << MBB->getNumber();
+}