continue;
if (DefMI->getOperand(0).getSubReg())
continue;
- unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
+ // FIXME: We should trivially coalesce subregister copies to expose CSE
+ // opportunities on instructions with truncated operands (see
+ // cse-add-with-overflow.ll). This can be done here as follows:
+ // if (SrcSubReg)
+ // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
+ // SrcSubReg);
+ // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+ //
+ // The 2-addr pass has been updated to handle coalesced subregs. However,
+ // some machine-specific code still can't handle it.
+ // To handle it properly we also need a way find a constrained subregister
+ // class given a super-reg class and subreg index.
+ if (DefMI->getOperand(1).getSubReg())
+ continue;
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- if (SrcSubReg)
- RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
- SrcSubReg);
if (!MRI->constrainRegClass(SrcReg, RC))
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
- MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+ MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
DefMI->eraseFromParent();
++NumCoalesces;
// Next, collect all defs into PhysDefs. If any is already in PhysRefs
// (which currently contains only uses), set the PhysUseDef flag.
PhysUseDef = false;
- MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
+ MachineBasicBlock::const_iterator I = MI; I = std::next(I);
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef())
}
CrossMBB = true;
}
- MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
+ MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
MachineBasicBlock::const_iterator E = MI;
MachineBasicBlock::const_iterator EE = CSMBB->end();
unsigned LookAheadLeft = LookAheadLimit;