- Rename AnalysisUsage::preservesAll to getPreservesAll & preservesCFG to

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 4fc373065881b8da2ff355099dcd77d5cbfccd98..02c25fdd7fbc08382d029ddacbed5b7d41ad933b 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -1,25 +1,12 @@
-// $Id$
-//***************************************************************************
-// File:
-//     MachineInstr.cpp
+//===-- MachineInstr.cpp --------------------------------------------------===//
 // 
-// Purpose:
-//     
-// 
-// Strategy:
-// 
-// History:
-//     7/2/01   -  Vikram Adve  -  Created
-//**************************************************************************/
+//===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Value.h"
-#include <iostream>
 using std::cerr;
 
 
-//************************ Class Implementations **************************/
-
 // Constructor for instructions with fixed #operands (nearly all)
 MachineInstr::MachineInstr(MachineOpCode _opCode,
                           OpCodeMask    _opCodeMask)
@@ -40,12 +27,28 @@ MachineInstr::MachineInstr(MachineOpCode _opCode,
 {
 }
 
+// 
+// Support for replacing opcode and operands of a MachineInstr in place.
+// This only resets the size of the operand vector and initializes it.
+// The new operands must be set explicitly later.
+// 
+void
+MachineInstr::replace(MachineOpCode _opCode,
+                      unsigned     numOperands,
+                      OpCodeMask    _opCodeMask)
+{
+  opCode = _opCode;
+  opCodeMask = _opCodeMask;
+  operands.clear();
+  operands.resize(numOperands);
+}
+
 void
 MachineInstr::SetMachineOperandVal(unsigned int i,
                                    MachineOperand::MachineOperandType opType,
                                    Value* _val,
-                                   bool isdef=false,
-                                   bool isDefAndUse=false)
+                                   bool isdef,
+                                   bool isDefAndUse)
 {
   assert(i < operands.size());
   operands[i].Initialize(opType, _val);
@@ -69,9 +72,9 @@ MachineInstr::SetMachineOperandConst(unsigned int i,
 void
 MachineInstr::SetMachineOperandReg(unsigned int i,
                                    int regNum,
-                                   bool isdef=false,
-                                   bool isDefAndUse=false,
-                                   bool isCCReg=false)
+                                   bool isdef,
+                                   bool isDefAndUse,
+                                   bool isCCReg)
 {
   assert(i < operands.size());
   operands[i].InitializeReg(regNum, isCCReg);
@@ -90,14 +93,43 @@ MachineInstr::SetRegForOperand(unsigned i, int regNum)
 }
 
 
+// Subsitute all occurrences of Value* oldVal with newVal in all operands
+// and all implicit refs.  If defsOnly == true, substitute defs only.
+unsigned
+MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
+{
+  unsigned numSubst = 0;
+
+  // Subsitute operands
+  for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
+    if (*O == oldVal)
+      if (!defsOnly || O.isDef())
+        {
+          O.getMachineOperand().value = newVal;
+          ++numSubst;
+        }
+
+  // Subsitute implicit refs
+  for (unsigned i=0, N=implicitRefs.size(); i < N; ++i)
+    if (implicitRefs[i] == oldVal)
+      if (!defsOnly || implicitRefIsDefined(i))
+        {
+          implicitRefs[i] = newVal;
+          ++numSubst;
+        }
+
+  return numSubst;
+}
+
+
 void
 MachineInstr::dump() const 
 {
   cerr << "  " << *this;
 }
 
-static inline std::ostream &OutputValue(std::ostream &os,
-                                        const Value* val)
+static inline std::ostream&
+OutputValue(std::ostream &os, const Value* val)
 {
   os << "(val ";
   if (val && val->hasName())
@@ -106,6 +138,12 @@ static inline std::ostream &OutputValue(std::ostream &os,
     return os << (void*) val << ")";              // print address only
 }
 
+static inline std::ostream&
+OutputReg(std::ostream &os, unsigned int regNum)
+{
+  return os << "%mreg(" << regNum << ")";
+}
+
 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
 {
   os << TargetInstrDescriptors[minstr.opCode].opCodeString;
@@ -149,14 +187,17 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
     case MachineOperand::MO_VirtualRegister:
       os << "%reg";
       OutputValue(os, mop.getVRegValue());
+      if (mop.hasAllocatedReg())
+        os << "==" << OutputReg(os, mop.getAllocatedRegNum());
       break;
     case MachineOperand::MO_CCRegister:
       os << "%ccreg";
       OutputValue(os, mop.getVRegValue());
+      if (mop.hasAllocatedReg())
+        os << "==" << OutputReg(os, mop.getAllocatedRegNum());
       break;
     case MachineOperand::MO_MachineRegister:
-      os << "%reg";
-      os << "(" << mop.getMachineRegNum() << ")";
+      OutputReg(os, mop.getMachineRegNum());
       break;
     case MachineOperand::MO_SignExtendedImmed:
       os << (long)mop.immedVal;