-// $Id$
-//***************************************************************************
-// File:
-// MachineInstr.cpp
+//===-- MachineInstr.cpp --------------------------------------------------===//
//
-// Purpose:
-//
-//
-// Strategy:
-//
-// History:
-// 7/2/01 - Vikram Adve - Created
-//**************************************************************************/
+//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Value.h"
-#include <iostream>
using std::cerr;
-//************************ Class Implementations **************************/
-
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode,
OpCodeMask _opCodeMask)
{
}
+//
+// Support for replacing opcode and operands of a MachineInstr in place.
+// This only resets the size of the operand vector and initializes it.
+// The new operands must be set explicitly later.
+//
+void
+MachineInstr::replace(MachineOpCode _opCode,
+ unsigned numOperands,
+ OpCodeMask _opCodeMask)
+{
+ opCode = _opCode;
+ opCodeMask = _opCodeMask;
+ operands.clear();
+ operands.resize(numOperands);
+}
+
void
MachineInstr::SetMachineOperandVal(unsigned int i,
- MachineOperand::MachineOperandType operandType,
- Value* _val, bool isdef=false)
+ MachineOperand::MachineOperandType opType,
+ Value* _val,
+ bool isdef,
+ bool isDefAndUse)
{
assert(i < operands.size());
- operands[i].Initialize(operandType, _val);
- operands[i].isDef = isdef ||
- TargetInstrDescriptors[opCode].resultPos == (int) i;
+ operands[i].Initialize(opType, _val);
+ if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
+ operands[i].markDef();
+ if (isDefAndUse)
+ operands[i].markDefAndUse();
}
void
assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
"immed. constant cannot be defined");
operands[i].InitializeConst(operandType, intValue);
- operands[i].isDef = false;
}
void
MachineInstr::SetMachineOperandReg(unsigned int i,
int regNum,
- bool isdef=false,
- bool isCCReg=false)
+ bool isdef,
+ bool isDefAndUse,
+ bool isCCReg)
{
assert(i < operands.size());
operands[i].InitializeReg(regNum, isCCReg);
- operands[i].isDef = isdef ||
- TargetInstrDescriptors[opCode].resultPos == (int) i;
+ if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
+ operands[i].markDef();
+ if (isDefAndUse)
+ operands[i].markDefAndUse();
+ regsUsed.insert(regNum);
}
void
-MachineInstr::dump(unsigned int indent) const
+MachineInstr::SetRegForOperand(unsigned i, int regNum)
{
- for (unsigned i=0; i < indent; i++)
- cerr << " ";
-
- cerr << *this;
+ operands[i].setRegForValue(regNum);
+ regsUsed.insert(regNum);
+}
+
+
+// Subsitute all occurrences of Value* oldVal with newVal in all operands
+// and all implicit refs. If defsOnly == true, substitute defs only.
+unsigned
+MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
+{
+ unsigned numSubst = 0;
+
+ // Subsitute operands
+ for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
+ if (*O == oldVal)
+ if (!defsOnly || O.isDef())
+ {
+ O.getMachineOperand().value = newVal;
+ ++numSubst;
+ }
+
+ // Subsitute implicit refs
+ for (unsigned i=0, N=implicitRefs.size(); i < N; ++i)
+ if (implicitRefs[i] == oldVal)
+ if (!defsOnly || implicitRefIsDefined(i))
+ {
+ implicitRefs[i] = newVal;
+ ++numSubst;
+ }
+
+ return numSubst;
+}
+
+
+void
+MachineInstr::dump() const
+{
+ cerr << " " << *this;
+}
+
+static inline std::ostream&
+OutputValue(std::ostream &os, const Value* val)
+{
+ os << "(val ";
+ if (val && val->hasName())
+ return os << val->getName() << ")";
+ else
+ return os << (void*) val << ")"; // print address only
+}
+
+static inline std::ostream&
+OutputReg(std::ostream &os, unsigned int regNum)
+{
+ return os << "%mreg(" << regNum << ")";
}
std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
os << "\t" << minstr.getOperand(i);
- if( minstr.getOperand(i).opIsDef() )
+ if( minstr.operandIsDefined(i) )
+ os << "*";
+ if( minstr.operandIsDefinedAndUsed(i) )
os << "*";
}
-#undef DEBUG_VAL_OP_ITERATOR
-#ifdef DEBUG_VAL_OP_ITERATOR
- os << "\n\tValue operands are: ";
- for (MachineInstr::val_const_op_iterator vo(&minstr); ! vo.done(); ++vo)
- {
- const Value* val = *vo;
- os << val << (vo.isDef()? "(def), " : ", ");
- }
-#endif
-
-
-
-#if 1
// code for printing implict references
-
unsigned NumOfImpRefs = minstr.getNumImplicitRefs();
if( NumOfImpRefs > 0 ) {
-
- os << "\tImplicit:";
-
+ os << "\tImplicit: ";
for(unsigned z=0; z < NumOfImpRefs; z++) {
- os << minstr.getImplicitRef(z);
+ OutputValue(os, minstr.getImplicitRef(z));
if( minstr.implicitRefIsDefined(z)) os << "*";
+ if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
os << "\t";
}
}
-
-#endif
+
return os << "\n";
}
-static inline std::ostream &OutputOperand(std::ostream &os,
- const MachineOperand &mop)
-{
- Value* val;
- switch (mop.getOperandType())
- {
- case MachineOperand::MO_CCRegister:
- case MachineOperand::MO_VirtualRegister:
- val = mop.getVRegValue();
- os << "(val ";
- if (val && val->hasName())
- os << val->getName();
- else
- os << val;
- return os << ")";
- case MachineOperand::MO_MachineRegister:
- return os << "(" << mop.getMachineRegNum() << ")";
- default:
- assert(0 && "Unknown operand type");
- return os;
- }
-}
-
-
std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
{
+ if (mop.opHiBits32())
+ os << "%lm(";
+ else if (mop.opLoBits32())
+ os << "%lo(";
+ else if (mop.opHiBits64())
+ os << "%hh(";
+ else if (mop.opLoBits64())
+ os << "%hm(";
+
switch(mop.opType)
{
case MachineOperand::MO_VirtualRegister:
- case MachineOperand::MO_MachineRegister:
os << "%reg";
- return OutputOperand(os, mop);
+ OutputValue(os, mop.getVRegValue());
+ if (mop.hasAllocatedReg())
+ os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+ break;
case MachineOperand::MO_CCRegister:
os << "%ccreg";
- return OutputOperand(os, mop);
+ OutputValue(os, mop.getVRegValue());
+ if (mop.hasAllocatedReg())
+ os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+ break;
+ case MachineOperand::MO_MachineRegister:
+ OutputReg(os, mop.getMachineRegNum());
+ break;
case MachineOperand::MO_SignExtendedImmed:
- return os << (long)mop.immedVal;
+ os << (long)mop.immedVal;
+ break;
case MachineOperand::MO_UnextendedImmed:
- return os << (long)mop.immedVal;
+ os << (long)mop.immedVal;
+ break;
case MachineOperand::MO_PCRelativeDisp:
{
const Value* opVal = mop.getVRegValue();
if (opVal->hasName())
os << opVal->getName();
else
- os << opVal;
- return os << ")";
+ os << (const void*) opVal;
+ os << ")";
+ break;
}
default:
assert(0 && "Unrecognized operand type");
break;
}
+ if (mop.flags &
+ (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
+ MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
+ os << ")";
+
return os;
}
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