Make sure to include name information if we have it

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 1fde26a1b06efd41f869c2a62263088b25187e0a..28fbd2d00483acb21b39520cf452e722444f7485 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -5,8 +5,9 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Value.h"
-#include "llvm/Target/MachineInstrInfo.h"  // FIXME: shouldn't need this!
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/MRegisterInfo.h"
 using std::cerr;
 
 // Global variable holding an array of descriptors for machine instructions.
@@ -191,14 +192,20 @@ OutputValue(std::ostream &os, const Value* val)
     return os << (void*) val << ")";              // print address only
 }
 
-static inline std::ostream&
-OutputReg(std::ostream &os, unsigned int regNum)
-{
-  return os << "%mreg(" << regNum << ")";
+static inline void OutputReg(std::ostream &os, unsigned RegNo,
+                             const MRegisterInfo *MRI = 0) {
+  if (MRI) {
+    if (RegNo < MRegisterInfo::FirstVirtualRegister)
+      os << "%" << MRI->get(RegNo).Name;
+    else
+      os << "%reg" << RegNo;
+  } else
+    os << "%mreg(" << RegNo << ")";
 }
 
 static void print(const MachineOperand &MO, std::ostream &OS,
                   const TargetMachine &TM) {
+  const MRegisterInfo *MRI = TM.getRegisterInfo();
   bool CloseParen = true;
   if (MO.opHiBits32())
     OS << "%lm(";
@@ -220,18 +227,18 @@ static void print(const MachineOperand &MO, std::ostream &OS,
         OS << "==";
     }
     if (MO.hasAllocatedReg())
-      OutputReg(OS, MO.getAllocatedRegNum());
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
     break;
   case MachineOperand::MO_CCRegister:
     OS << "%ccreg";
     OutputValue(OS, MO.getVRegValue());
     if (MO.hasAllocatedReg()) {
       OS << "==";
-      OutputReg(OS, MO.getAllocatedRegNum());
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
     }
     break;
   case MachineOperand::MO_MachineRegister:
-    OutputReg(OS, MO.getMachineRegNum());
+    OutputReg(OS, MO.getMachineRegNum(), MRI);
     break;
   case MachineOperand::MO_SignExtendedImmed:
     OS << (long)MO.getImmedValue();
@@ -259,17 +266,28 @@ static void print(const MachineOperand &MO, std::ostream &OS,
 }
 
 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
+  unsigned StartOp = 0;
+
+   // Specialize printing if op#0 is definition
+  if (getNumOperands() && operandIsDefined(0)) {
+    ::print(getOperand(0), OS, TM);
+    OS << " = ";
+    ++StartOp;   // Don't print this operand again!
+  }
   OS << TM.getInstrInfo().getName(getOpcode());
-  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    OS << "\t";
+  
+  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
+    if (i != StartOp)
+      OS << ",";
+    OS << " ";
     ::print(getOperand(i), OS, TM);
-
+    
     if (operandIsDefinedAndUsed(i))
       OS << "<def&use>";
     else if (operandIsDefined(i))
       OS << "<def>";
   }
-
+    
   // code for printing implict references
   if (getNumImplicitRefs()) {
     OS << "\tImplicitRefs: ";