Make sure to include name information if we have it

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 605fe16c9b114dc67c294f1420ea293cf8a0f11c..28fbd2d00483acb21b39520cf452e722444f7485 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -5,7 +5,9 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Value.h"
-#include "llvm/Target/MachineInstrInfo.h"  // FIXME: shouldn't need this!
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/MRegisterInfo.h"
 using std::cerr;
 
 // Global variable holding an array of descriptors for machine instructions.
@@ -190,12 +192,119 @@ OutputValue(std::ostream &os, const Value* val)
     return os << (void*) val << ")";              // print address only
 }
 
-static inline std::ostream&
-OutputReg(std::ostream &os, unsigned int regNum)
-{
-  return os << "%mreg(" << regNum << ")";
+static inline void OutputReg(std::ostream &os, unsigned RegNo,
+                             const MRegisterInfo *MRI = 0) {
+  if (MRI) {
+    if (RegNo < MRegisterInfo::FirstVirtualRegister)
+      os << "%" << MRI->get(RegNo).Name;
+    else
+      os << "%reg" << RegNo;
+  } else
+    os << "%mreg(" << RegNo << ")";
+}
+
+static void print(const MachineOperand &MO, std::ostream &OS,
+                  const TargetMachine &TM) {
+  const MRegisterInfo *MRI = TM.getRegisterInfo();
+  bool CloseParen = true;
+  if (MO.opHiBits32())
+    OS << "%lm(";
+  else if (MO.opLoBits32())
+    OS << "%lo(";
+  else if (MO.opHiBits64())
+    OS << "%hh(";
+  else if (MO.opLoBits64())
+    OS << "%hm(";
+  else
+    CloseParen = false;
+  
+  switch (MO.getType()) {
+  case MachineOperand::MO_VirtualRegister:
+    if (MO.getVRegValue()) {
+      OS << "%reg";
+      OutputValue(OS, MO.getVRegValue());
+      if (MO.hasAllocatedReg())
+        OS << "==";
+    }
+    if (MO.hasAllocatedReg())
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+    break;
+  case MachineOperand::MO_CCRegister:
+    OS << "%ccreg";
+    OutputValue(OS, MO.getVRegValue());
+    if (MO.hasAllocatedReg()) {
+      OS << "==";
+      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+    }
+    break;
+  case MachineOperand::MO_MachineRegister:
+    OutputReg(OS, MO.getMachineRegNum(), MRI);
+    break;
+  case MachineOperand::MO_SignExtendedImmed:
+    OS << (long)MO.getImmedValue();
+    break;
+  case MachineOperand::MO_UnextendedImmed:
+    OS << (long)MO.getImmedValue();
+    break;
+  case MachineOperand::MO_PCRelativeDisp: {
+    const Value* opVal = MO.getVRegValue();
+    bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
+    OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
+    if (opVal->hasName())
+      OS << opVal->getName();
+    else
+      OS << (const void*) opVal;
+    OS << ")";
+    break;
+  }
+  default:
+    assert(0 && "Unrecognized operand type");
+  }
+
+  if (CloseParen)
+    OS << ")";
+}
+
+void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
+  unsigned StartOp = 0;
+
+   // Specialize printing if op#0 is definition
+  if (getNumOperands() && operandIsDefined(0)) {
+    ::print(getOperand(0), OS, TM);
+    OS << " = ";
+    ++StartOp;   // Don't print this operand again!
+  }
+  OS << TM.getInstrInfo().getName(getOpcode());
+  
+  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
+    if (i != StartOp)
+      OS << ",";
+    OS << " ";
+    ::print(getOperand(i), OS, TM);
+    
+    if (operandIsDefinedAndUsed(i))
+      OS << "<def&use>";
+    else if (operandIsDefined(i))
+      OS << "<def>";
+  }
+    
+  // code for printing implict references
+  if (getNumImplicitRefs()) {
+    OS << "\tImplicitRefs: ";
+    for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
+      OS << "\t";
+      OutputValue(OS, getImplicitRef(i)); 
+      if (implicitRefIsDefinedAndUsed(i))
+        OS << "<def&use>";
+      else if (implicitRefIsDefined(i))
+        OS << "<def>";
+    }
+  }
+  
+  OS << "\n";
 }
 
+
 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
 {
   os << TargetInstrDescriptors[minstr.opCode].Name;
@@ -234,28 +343,32 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
   else if (mop.opLoBits64())
     os << "%hm(";
   
-  switch(mop.opType)
+  switch (mop.getType())
     {
     case MachineOperand::MO_VirtualRegister:
       os << "%reg";
       OutputValue(os, mop.getVRegValue());
-      if (mop.hasAllocatedReg())
-        os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+      if (mop.hasAllocatedReg()) {
+        os << "==";
+        OutputReg(os, mop.getAllocatedRegNum());
+      }
       break;
     case MachineOperand::MO_CCRegister:
       os << "%ccreg";
       OutputValue(os, mop.getVRegValue());
-      if (mop.hasAllocatedReg())
-        os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+      if (mop.hasAllocatedReg()) {
+        os << "==";
+        OutputReg(os, mop.getAllocatedRegNum());
+      }
       break;
     case MachineOperand::MO_MachineRegister:
       OutputReg(os, mop.getMachineRegNum());
       break;
     case MachineOperand::MO_SignExtendedImmed:
-      os << (long)mop.immedVal;
+      os << (long)mop.getImmedValue();
       break;
     case MachineOperand::MO_UnextendedImmed:
-      os << (long)mop.immedVal;
+      os << (long)mop.getImmedValue();
       break;
     case MachineOperand::MO_PCRelativeDisp:
       {