//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Value.h"
-#include "llvm/Target/MachineInstrInfo.h" // FIXME: shouldn't need this!
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/MRegisterInfo.h"
using std::cerr;
+// Global variable holding an array of descriptors for machine instructions.
+// The actual object needs to be created separately for each target machine.
+// This variable is initialized and reset by class MachineInstrInfo.
+//
+// FIXME: This should be a property of the target so that more than one target
+// at a time can be active...
+//
+extern const MachineInstrDescriptor *TargetInstrDescriptors;
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode)
- : opCode(_opCode), opCodeMask(0),
- operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()) {
+ : opCode(_opCode),
+ operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
+ numImplicitRefs(0)
+{
assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
}
// Constructor for instructions with variable #operands
MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
- : opCode(OpCode), opCodeMask(0), operands(numOperands, MachineOperand()) {
+ : opCode(OpCode),
+ operands(numOperands, MachineOperand()),
+ numImplicitRefs(0)
+{
}
+/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
+/// not a resize for them. It is expected that if you use this that you call
+/// add* methods below to fill up the operands, instead of the Set methods.
+/// Eventually, the "resizing" ctors will be phased out.
+///
MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
- bool XX, bool YY) : opCode(Opcode), opCodeMask(0) {
+ bool XX, bool YY)
+ : opCode(Opcode),
+ numImplicitRefs(0)
+{
operands.reserve(numOperands);
}
+/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
+/// MachineInstr is created and added to the end of the specified basic block.
+///
+MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
+ unsigned numOperands)
+ : opCode(Opcode),
+ numImplicitRefs(0)
+{
+ assert(MBB && "Cannot use inserting ctor with null basic block!");
+ operands.reserve(numOperands);
+ MBB->push_back(this); // Add instruction to end of basic block!
+}
+
+
// OperandComplete - Return true if it's illegal to add a new operand
-bool MachineInstr::OperandsComplete() const {
+bool MachineInstr::OperandsComplete() const
+{
int NumOperands = TargetInstrDescriptors[opCode].numOperands;
- if (NumOperands >= 0 && operands.size() >= (unsigned)NumOperands)
+ if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
return true; // Broken!
return false;
}
// This only resets the size of the operand vector and initializes it.
// The new operands must be set explicitly later.
//
-void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands) {
+void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
+{
+ assert(getNumImplicitRefs() == 0 &&
+ "This is probably broken because implicit refs are going to be lost.");
opCode = Opcode;
- opCodeMask = 0;
operands.clear();
operands.resize(numOperands, MachineOperand());
}
bool isdef,
bool isDefAndUse)
{
- assert(i < operands.size());
+ assert(i < operands.size()); // may be explicit or implicit op
operands[i].opType = opType;
operands[i].value = V;
operands[i].regNum = -1;
MachineOperand::MachineOperandType operandType,
int64_t intValue)
{
- assert(i < operands.size());
+ assert(i < getNumOperands()); // must be explicit op
assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
"immed. constant cannot be defined");
MachineInstr::SetMachineOperandReg(unsigned i,
int regNum,
bool isdef) {
- assert(i < operands.size());
+ assert(i < getNumOperands()); // must be explicit op
operands[i].opType = MachineOperand::MO_MachineRegister;
operands[i].value = NULL;
void
MachineInstr::SetRegForOperand(unsigned i, int regNum)
{
+ assert(i < getNumOperands()); // must be explicit op
operands[i].setRegForValue(regNum);
insertUsedReg(regNum);
}
}
// Subsitute implicit refs
- for (unsigned i=0, N=implicitRefs.size(); i < N; ++i)
+ for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
if (!defsOnly || implicitRefIsDefined(i))
{
- implicitRefs[i].Val = newVal;
+ getImplicitOp(i).value = newVal;
++numSubst;
}
return os << (void*) val << ")"; // print address only
}
-static inline std::ostream&
-OutputReg(std::ostream &os, unsigned int regNum)
-{
- return os << "%mreg(" << regNum << ")";
+static inline void OutputReg(std::ostream &os, unsigned RegNo,
+ const MRegisterInfo *MRI = 0) {
+ if (MRI) {
+ if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ os << "%" << MRI->get(RegNo).Name;
+ else
+ os << "%reg" << RegNo;
+ } else
+ os << "%mreg(" << RegNo << ")";
}
+static void print(const MachineOperand &MO, std::ostream &OS,
+ const TargetMachine &TM) {
+ const MRegisterInfo *MRI = TM.getRegisterInfo();
+ bool CloseParen = true;
+ if (MO.opHiBits32())
+ OS << "%lm(";
+ else if (MO.opLoBits32())
+ OS << "%lo(";
+ else if (MO.opHiBits64())
+ OS << "%hh(";
+ else if (MO.opLoBits64())
+ OS << "%hm(";
+ else
+ CloseParen = false;
+
+ switch (MO.getType()) {
+ case MachineOperand::MO_VirtualRegister:
+ if (MO.getVRegValue()) {
+ OS << "%reg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg())
+ OS << "==";
+ }
+ if (MO.hasAllocatedReg())
+ OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ break;
+ case MachineOperand::MO_CCRegister:
+ OS << "%ccreg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg()) {
+ OS << "==";
+ OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ }
+ break;
+ case MachineOperand::MO_MachineRegister:
+ OutputReg(OS, MO.getMachineRegNum(), MRI);
+ break;
+ case MachineOperand::MO_SignExtendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_UnextendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_PCRelativeDisp: {
+ const Value* opVal = MO.getVRegValue();
+ bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
+ OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
+ if (opVal->hasName())
+ OS << opVal->getName();
+ else
+ OS << (const void*) opVal;
+ OS << ")";
+ break;
+ }
+ default:
+ assert(0 && "Unrecognized operand type");
+ }
+
+ if (CloseParen)
+ OS << ")";
+}
+
+void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
+ unsigned StartOp = 0;
+
+ // Specialize printing if op#0 is definition
+ if (getNumOperands() && operandIsDefined(0)) {
+ ::print(getOperand(0), OS, TM);
+ OS << " = ";
+ ++StartOp; // Don't print this operand again!
+ }
+ OS << TM.getInstrInfo().getName(getOpcode());
+
+ for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
+ if (i != StartOp)
+ OS << ",";
+ OS << " ";
+ ::print(getOperand(i), OS, TM);
+
+ if (operandIsDefinedAndUsed(i))
+ OS << "<def&use>";
+ else if (operandIsDefined(i))
+ OS << "<def>";
+ }
+
+ // code for printing implict references
+ if (getNumImplicitRefs()) {
+ OS << "\tImplicitRefs: ";
+ for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
+ OS << "\t";
+ OutputValue(OS, getImplicitRef(i));
+ if (implicitRefIsDefinedAndUsed(i))
+ OS << "<def&use>";
+ else if (implicitRefIsDefined(i))
+ OS << "<def>";
+ }
+ }
+
+ OS << "\n";
+}
+
+
std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
{
- os << TargetInstrDescriptors[minstr.opCode].opCodeString;
+ os << TargetInstrDescriptors[minstr.opCode].Name;
for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
os << "\t" << minstr.getOperand(i);
else if (mop.opLoBits64())
os << "%hm(";
- switch(mop.opType)
+ switch (mop.getType())
{
case MachineOperand::MO_VirtualRegister:
os << "%reg";
OutputValue(os, mop.getVRegValue());
- if (mop.hasAllocatedReg())
- os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+ if (mop.hasAllocatedReg()) {
+ os << "==";
+ OutputReg(os, mop.getAllocatedRegNum());
+ }
break;
case MachineOperand::MO_CCRegister:
os << "%ccreg";
OutputValue(os, mop.getVRegValue());
- if (mop.hasAllocatedReg())
- os << "==" << OutputReg(os, mop.getAllocatedRegNum());
+ if (mop.hasAllocatedReg()) {
+ os << "==";
+ OutputReg(os, mop.getAllocatedRegNum());
+ }
break;
case MachineOperand::MO_MachineRegister:
OutputReg(os, mop.getMachineRegNum());
break;
case MachineOperand::MO_SignExtendedImmed:
- os << (long)mop.immedVal;
+ os << (long)mop.getImmedValue();
break;
case MachineOperand::MO_UnextendedImmed:
- os << (long)mop.immedVal;
+ os << (long)mop.getImmedValue();
break;
case MachineOperand::MO_PCRelativeDisp:
{
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