There should be no extending loads or truncating

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index da8101f6a08bb011aa0f0e3eadd2b9d705e4dc9d..36212ba4d068f794673051876228dba22edc98e7 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -17,7 +17,6 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetInstrDesc.h"
@@ -246,6 +245,7 @@ MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
                                      int64_t o, uint64_t s, unsigned int a)
   : Offset(o), Size(s), V(v),
     Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
+  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
 }
 
 //===----------------------------------------------------------------------===//
@@ -347,8 +347,7 @@ int MachineInstr::getOpcode() const {
 /// return null.
 MachineRegisterInfo *MachineInstr::getRegInfo() {
   if (MachineBasicBlock *MBB = getParent())
-    if (MachineFunction *MF = MBB->getParent())
-      return &MF->getRegInfo();
+    return &MBB->getParent()->getRegInfo();
   return 0;
 }
 
@@ -623,20 +622,15 @@ int MachineInstr::findFirstPredOperandIdx() const {
   return -1;
 }
   
-/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
-/// to two addr elimination.
-bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
+/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
+/// check if the register def is a re-definition due to two addr elimination.
+bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
   const TargetInstrDesc &TID = getDesc();
-  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    const MachineOperand &MO1 = getOperand(i);
-    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
-      for (unsigned j = i+1; j < e; ++j) {
-        const MachineOperand &MO2 = getOperand(j);
-        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
-            TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
-          return true;
-      }
-    }
+  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = getOperand(i);
+    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
+        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
+      return true;
   }
   return false;
 }