#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
-#include "Support/LeakDetector.h"
+#include "llvm/Support/LeakDetector.h"
+#include <iostream>
+
using namespace llvm;
// Global variable holding an array of descriptors for machine instructions.
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
-namespace {
+namespace llvm {
extern const TargetInstrDescriptor *TargetInstrDescriptors;
}
MBB->push_back(this); // Add instruction to end of basic block!
}
-MachineInstr::~MachineInstr()
-{
+/// MachineInstr ctor - Copies MachineInstr arg exactly
+///
+MachineInstr::MachineInstr(const MachineInstr &MI) {
+ Opcode = MI.getOpcode();
+ numImplicitRefs = MI.getNumImplicitRefs();
+ operands.reserve(MI.getNumOperands());
+
+ // Add operands
+ for (unsigned i = 0; i < MI.getNumOperands(); ++i)
+ operands.push_back(MachineOperand(MI.getOperand(i)));
+
+ // Set parent, next, and prev to null
+ parent = 0;
+ prev = 0;
+ next = 0;
+}
+
+
+MachineInstr::~MachineInstr() {
LeakDetector::removeGarbageObject(this);
}
+/// clone - Create a copy of 'this' instruction that is identical in all ways
+/// except the following: the new instruction has no parent and it has no name
+///
+MachineInstr* MachineInstr::clone() const {
+ return new MachineInstr(*this);
+}
+
/// OperandComplete - Return true if it's illegal to add a new operand
///
bool MachineInstr::OperandsComplete() const {
Value* V) {
assert(i < operands.size()); // may be explicit or implicit op
operands[i].opType = opTy;
- operands[i].value = V;
- operands[i].regNum = -1;
+ operands[i].contents.value = V;
+ operands[i].extra.regNum = -1;
}
void
MachineInstr::SetMachineOperandConst(unsigned i,
MachineOperand::MachineOperandType opTy,
- int64_t intValue) {
+ int intValue) {
assert(i < getNumOperands()); // must be explicit op
assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
"immed. constant cannot be defined");
operands[i].opType = opTy;
- operands[i].value = NULL;
- operands[i].immedVal = intValue;
- operands[i].regNum = -1;
+ operands[i].contents.value = NULL;
+ operands[i].contents.immedVal = intValue;
+ operands[i].extra.regNum = -1;
operands[i].flags = 0;
}
assert(i < getNumOperands()); // must be explicit op
operands[i].opType = MachineOperand::MO_MachineRegister;
- operands[i].value = NULL;
- operands[i].regNum = regNum;
+ operands[i].contents.value = NULL;
+ operands[i].extra.regNum = regNum;
}
// Used only by the SPARC back-end.
if (!defsOnly ||
notDefsAndUses && (O.isDef() && !O.isUse()) ||
!notDefsAndUses && O.isDef())
- {
- O.getMachineOperand().value = newVal;
- ++numSubst;
- }
- else
+ {
+ O.getMachineOperand().contents.value = newVal;
+ ++numSubst;
+ } else
someArgsWereIgnored = true;
// Substitute implicit refs
- for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
- if (getImplicitRef(i) == oldVal)
+ for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
+ if (getImplicitRef(i) == oldVal) {
+ MachineOperand Op = getImplicitOp(i);
if (!defsOnly ||
- notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
- !notDefsAndUses && getImplicitOp(i).isDef())
- {
- getImplicitOp(i).value = newVal;
- ++numSubst;
- }
- else
+ notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
+ !notDefsAndUses && Op.isDef())
+ {
+ Op.contents.value = newVal;
+ ++numSubst;
+ } else
someArgsWereIgnored = true;
-
+ }
return numSubst;
}
static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
os << "(val ";
- os << (void*) val; // print address always
+ os << (void*) val; // print address always
if (val && val->hasName())
- os << " " << val->getName(); // print name also, if available
+ os << " " << val->getName(); // print name also, if available
os << ")";
return os;
}
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
- if (MRegisterInfo::isPhysicalRegister(RegNo)) {
+ if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
if (MRI)
os << "%" << MRI->get(RegNo).Name;
else
}
static void print(const MachineOperand &MO, std::ostream &OS,
- const TargetMachine &TM) {
- const MRegisterInfo *MRI = TM.getRegisterInfo();
+ const TargetMachine *TM) {
+ const MRegisterInfo *MRI = 0;
+
+ if (TM) MRI = TM->getRegisterInfo();
+
bool CloseParen = true;
if (MO.isHiBits32())
OS << "%lm(";
break;
}
case MachineOperand::MO_MachineBasicBlock:
- OS << "bb<"
+ OS << "mbb<"
<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
- << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
+ << "," << (void*)MO.getMachineBasicBlock() << ">";
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << MO.getFrameIndex() << ">";
OS << "<cp#" << MO.getConstantPoolIndex() << ">";
break;
case MachineOperand::MO_GlobalAddress:
- OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
+ OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
+ if (MO.getOffset()) OS << "+" << MO.getOffset();
+ OS << ">";
break;
case MachineOperand::MO_ExternalSymbol:
- OS << "<es:" << MO.getSymbolName() << ">";
+ OS << "<es:" << MO.getSymbolName();
+ if (MO.getOffset()) OS << "+" << MO.getOffset();
+ OS << ">";
break;
default:
assert(0 && "Unrecognized operand type");
OS << ")";
}
-void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
+void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
OS << " = ";
++StartOp; // Don't print this operand again!
}
- OS << TM.getInstrInfo().getName(getOpcode());
+
+ // Must check if Target machine is not null because machine BB could not
+ // be attached to a Machine function yet
+ if (TM)
+ OS << TM->getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
// code for printing implicit references
if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: ";
- for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
+ for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
OS << "\t";
OutputValue(OS, getImplicitRef(i));
if (getImplicitOp(i).isDef())
- if (getImplicitOp(i).isUse())
- OS << "<def&use>";
- else
- OS << "<def>";
+ if (getImplicitOp(i).isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
}
OS << "\n";
}
+namespace llvm {
std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
// If the instruction is embedded into a basic block, we can find the target
// info for the instruction.
if (const MachineBasicBlock *MBB = MI.getParent()) {
const MachineFunction *MF = MBB->getParent();
- MI.print(os, MF->getTarget());
+ if (MF)
+ MI.print(os, &MF->getTarget());
+ else
+ MI.print(os, 0);
return os;
}
// and such.
os << TargetInstrDescriptors[MI.getOpcode()].Name;
- for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
+ for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
if (MI.getOperand(i).isDef())
if (MI.getOperand(i).isUse())
unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) {
os << "\tImplicit: ";
- for (unsigned z=0; z < NumOfImpRefs; z++) {
+ for (unsigned z = 0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z));
if (MI.getImplicitOp(z).isDef())
if (MI.getImplicitOp(z).isUse())
else if (MO.isLoBits64())
OS << "%hm(";
- switch (MO.getType())
- {
- case MachineOperand::MO_VirtualRegister:
- if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getReg());
-
- if (MO.getVRegValue()) {
- if (MO.hasAllocatedReg()) OS << "==";
- OS << "%vreg";
- OutputValue(OS, MO.getVRegValue());
- }
- break;
- case MachineOperand::MO_CCRegister:
- OS << "%ccreg";
+ switch (MO.getType()) {
+ case MachineOperand::MO_VirtualRegister:
+ if (MO.hasAllocatedReg())
+ OutputReg(OS, MO.getReg());
+
+ if (MO.getVRegValue()) {
+ if (MO.hasAllocatedReg()) OS << "==";
+ OS << "%vreg";
OutputValue(OS, MO.getVRegValue());
- if (MO.hasAllocatedReg()) {
- OS << "==";
- OutputReg(OS, MO.getReg());
- }
- break;
- case MachineOperand::MO_MachineRegister:
- OutputReg(OS, MO.getMachineRegNum());
- break;
- case MachineOperand::MO_SignExtendedImmed:
- OS << (long)MO.getImmedValue();
- break;
- case MachineOperand::MO_UnextendedImmed:
- OS << (long)MO.getImmedValue();
- break;
- case MachineOperand::MO_PCRelativeDisp:
- {
- const Value* opVal = MO.getVRegValue();
- bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
- OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
- if (opVal->hasName())
- OS << opVal->getName();
- else
- OS << (const void*) opVal;
- OS << ")";
- break;
- }
- case MachineOperand::MO_MachineBasicBlock:
- OS << "bb<"
- << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
- << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
- break;
- case MachineOperand::MO_FrameIndex:
- OS << "<fi#" << MO.getFrameIndex() << ">";
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- OS << "<cp#" << MO.getConstantPoolIndex() << ">";
- break;
- case MachineOperand::MO_GlobalAddress:
- OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
- break;
- case MachineOperand::MO_ExternalSymbol:
- OS << "<es:" << MO.getSymbolName() << ">";
- break;
- default:
- assert(0 && "Unrecognized operand type");
- break;
}
+ break;
+ case MachineOperand::MO_CCRegister:
+ OS << "%ccreg";
+ OutputValue(OS, MO.getVRegValue());
+ if (MO.hasAllocatedReg()) {
+ OS << "==";
+ OutputReg(OS, MO.getReg());
+ }
+ break;
+ case MachineOperand::MO_MachineRegister:
+ OutputReg(OS, MO.getMachineRegNum());
+ break;
+ case MachineOperand::MO_SignExtendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_UnextendedImmed:
+ OS << (long)MO.getImmedValue();
+ break;
+ case MachineOperand::MO_PCRelativeDisp: {
+ const Value* opVal = MO.getVRegValue();
+ bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
+ OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
+ if (opVal->hasName())
+ OS << opVal->getName();
+ else
+ OS << (const void*) opVal;
+ OS << ")";
+ break;
+ }
+ case MachineOperand::MO_MachineBasicBlock:
+ OS << "<mbb:"
+ << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
+ << "@" << (void*)MO.getMachineBasicBlock() << ">";
+ break;
+ case MachineOperand::MO_FrameIndex:
+ OS << "<fi#" << MO.getFrameIndex() << ">";
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ OS << "<cp#" << MO.getConstantPoolIndex() << ">";
+ break;
+ case MachineOperand::MO_GlobalAddress:
+ OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
+ break;
+ case MachineOperand::MO_ExternalSymbol:
+ OS << "<es:" << MO.getSymbolName() << ">";
+ break;
+ default:
+ assert(0 && "Unrecognized operand type");
+ break;
+ }
if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")";
return OS;
}
+}
projects / oota-llvm.git / blobdiff