/// MachineRegisterInfo. If it is null, then the next/prev fields should be
/// explicitly nulled out.
void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
- assert(isRegister() && "Can only add reg operand to use lists");
+ assert(isReg() && "Can only add reg operand to use lists");
// If the reginfo pointer is null, just explicitly null out or next/prev
// pointers, to ensure they are not garbage.
void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
- if (isRegister() && getParent() && getParent()->getParent() &&
+ if (isReg() && getParent() && getParent()->getParent() &&
getParent()->getParent()->getParent())
RemoveRegOperandFromRegInfo();
bool isKill, bool isDead) {
// If this operand is already a register operand, use setReg to update the
// register's use/def lists.
- if (isRegister()) {
+ if (isReg()) {
assert(!isEarlyClobber());
setReg(Reg);
} else {
OS << "<";
bool NeedComma = false;
if (isImplicit()) {
+ if (NeedComma) OS << ",";
OS << (isDef() ? "imp-def" : "imp-use");
NeedComma = true;
} else if (isDef()) {
+ if (NeedComma) OS << ",";
if (isEarlyClobber())
OS << "earlyclobber,";
OS << "def";
#ifndef NDEBUG
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
- assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) &&
+ assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
"Reg operand def/use list corrupted");
}
#endif
/// operands already be on their use lists.
void MachineInstr::RemoveRegOperandsFromUseLists() {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
- if (Operands[i].isRegister())
+ if (Operands[i].isReg())
Operands[i].RemoveRegOperandFromRegInfo();
}
}
/// operands not be on their use lists yet.
void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
- if (Operands[i].isRegister())
+ if (Operands[i].isReg())
Operands[i].AddRegOperandToRegInfo(&RegInfo);
}
}
/// an explicit operand it is added at the end of the explicit operand list
/// (before the first implicit operand).
void MachineInstr::addOperand(const MachineOperand &Op) {
- bool isImpReg = Op.isRegister() && Op.isImplicit();
+ bool isImpReg = Op.isReg() && Op.isImplicit();
assert((isImpReg || !OperandsComplete()) &&
"Trying to add an operand to a machine instr that is already done!");
Operands.back().ParentMI = this;
// If the operand is a register, update the operand's use list.
- if (Op.isRegister())
+ if (Op.isReg())
Operands.back().AddRegOperandToRegInfo(getRegInfo());
return;
}
// Do explicitly set the reginfo for this operand though, to ensure the
// next/prev fields are properly nulled out.
- if (Operands[OpNo].isRegister())
+ if (Operands[OpNo].isReg())
Operands[OpNo].AddRegOperandToRegInfo(0);
} else if (Operands.size()+1 <= Operands.capacity()) {
// list, just remove the implicit operands, add the operand, then re-add all
// the rest of the operands.
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
- assert(Operands[i].isRegister() && "Should only be an implicit reg!");
+ assert(Operands[i].isReg() && "Should only be an implicit reg!");
Operands[i].RemoveRegOperandFromRegInfo();
}
Operands.insert(Operands.begin()+OpNo, Op);
Operands[OpNo].ParentMI = this;
- if (Operands[OpNo].isRegister())
+ if (Operands[OpNo].isReg())
Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
// Re-add all the implicit ops.
for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
- assert(Operands[i].isRegister() && "Should only be an implicit reg!");
+ assert(Operands[i].isReg() && "Should only be an implicit reg!");
Operands[i].AddRegOperandToRegInfo(RegInfo);
}
} else {
// Special case removing the last one.
if (OpNo == Operands.size()-1) {
// If needed, remove from the reg def/use list.
- if (Operands.back().isRegister() && Operands.back().isOnRegUseList())
+ if (Operands.back().isReg() && Operands.back().isOnRegUseList())
Operands.back().RemoveRegOperandFromRegInfo();
Operands.pop_back();
MachineRegisterInfo *RegInfo = getRegInfo();
if (RegInfo) {
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
- if (Operands[i].isRegister())
+ if (Operands[i].isReg())
Operands[i].RemoveRegOperandFromRegInfo();
}
}
if (RegInfo) {
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
- if (Operands[i].isRegister())
+ if (Operands[i].isReg())
Operands[i].AddRegOperandToRegInfo(RegInfo);
}
}
for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
const MachineOperand &MO = getOperand(NumOperands);
- if (!MO.isRegister() || !MO.isImplicit())
+ if (!MO.isReg() || !MO.isImplicit())
NumOperands++;
}
return NumOperands;
const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (!MO.isRegister() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (!MOReg)
const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (!MO.isRegister() || !MO.isDef())
+ if (!MO.isReg() || !MO.isDef())
continue;
unsigned MOReg = MO.getReg();
if (MOReg == Reg ||
const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
+ if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
return true;
}
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
+ if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
continue;
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
MachineOperand &MOp = getOperand(j);
// destination. The check for isInvariantLoad gives the targe the chance to
// classify the load as always returning a constant, e.g. a constant pool
// load.
- if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
+ if (TID->mayLoad() && !TII->isInvariantLoad(this))
// Otherwise, this is a real load. If there is a store between the load and
- // end of block, we can't sink the load.
- //
- // FIXME: we can't do this transformation until we know that the load is
- // not volatile, and machineinstrs don't keep this info. :(
- //
- //if (SawStore)
- return false;
- }
+ // end of block, or if the laod is volatile, we can't move it.
+ return !SawStore && !hasVolatileMemoryRef();
+
return true;
}
return false;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (!MO.isRegister())
+ if (!MO.isReg())
continue;
// FIXME: For now, do not remat any instruction with register operands.
// Later on, we can loosen the restriction is the register operands have
return true;
}
+/// hasVolatileMemoryRef - Return true if this instruction may have a
+/// volatile memory reference, or if the information describing the
+/// memory reference is not available. Return false if it is known to
+/// have no volatile memory references.
+bool MachineInstr::hasVolatileMemoryRef() const {
+ // An instruction known never to access memory won't have a volatile access.
+ if (!TID->mayStore() &&
+ !TID->mayLoad() &&
+ !TID->isCall() &&
+ !TID->hasUnmodeledSideEffects())
+ return false;
+
+ // Otherwise, if the instruction has no memory reference information,
+ // conservatively assume it wasn't preserved.
+ if (memoperands_empty())
+ return true;
+
+ // Check the memory reference information for volatile references.
+ for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
+ E = memoperands_end(); I != E; ++I)
+ if (I->isVolatile())
+ return true;
+
+ return false;
+}
+
void MachineInstr::dump() const {
cerr << " " << *this;
}
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
// Specialize printing if op#0 is definition
unsigned StartOp = 0;
- if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
+ if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
getOperand(0).print(OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (!MO.isRegister() || !MO.isUse())
+ if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (!Reg)
SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (!MO.isRegister() || !MO.isDef())
+ if (!MO.isReg() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
if (!Reg)
projects / oota-llvm.git / blobdiff