Enable re-materialization of instructions which have virtual register operands if

[oota-llvm.git] / lib / CodeGen / MachineInstr.cpp

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index e1e2336b5027bb109b380a1b6a7464ca09878c90..911d5caa1d331d5267a569acd336552d00db3582 100644 (file)
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -11,14 +11,17 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/Constants.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Value.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetInstrDesc.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Support/LeakDetector.h"
 #include "llvm/Support/Streams.h"
 #include <ostream>
@@ -136,6 +139,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
            getSubReg() == Other.getSubReg();
   case MachineOperand::MO_Immediate:
     return getImm() == Other.getImm();
+  case MachineOperand::MO_FPImmediate:
+    return getFPImm() == Other.getFPImm();
   case MachineOperand::MO_MachineBasicBlock:
     return getMBB() == Other.getMBB();
   case MachineOperand::MO_FrameIndex:
@@ -157,7 +162,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
   switch (getType()) {
   case MachineOperand::MO_Register:
-    if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
+    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
       OS << "%reg" << getReg();
     } else {
       // If the instruction is embedded into a basic block, we can find the
@@ -195,6 +200,13 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
   case MachineOperand::MO_Immediate:
     OS << getImm();
     break;
+  case MachineOperand::MO_FPImmediate:
+    if (getFPImm()->getType() == Type::FloatTy) {
+      OS << getFPImm()->getValueAPF().convertToFloat();
+    } else {
+      OS << getFPImm()->getValueAPF().convertToDouble();
+    }
+    break;
   case MachineOperand::MO_MachineBasicBlock:
     OS << "mbb<"
        << ((Value*)getMBB()->getBasicBlock())->getName()
@@ -292,6 +304,7 @@ MachineInstr::MachineInstr(const MachineInstr &MI) {
   TID = &MI.getDesc();
   NumImplicitOps = MI.NumImplicitOps;
   Operands.reserve(MI.getNumOperands());
+  MemOperands = MI.MemOperands;
 
   // Add operands
   for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
@@ -627,11 +640,43 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
     getOperand(i).print(OS, TM);
   }
 
+  if (getNumMemOperands() > 0) {
+    OS << ", Mem:";
+    for (unsigned i = 0; i < getNumMemOperands(); i++) {
+      const MemOperand &MRO = getMemOperand(i);
+      const Value *V = MRO.getValue();
+
+      assert((MRO.isLoad() || MRO.isStore()) &&
+             "SV has to be a load, store or both.");
+      
+      if (MRO.isVolatile())
+        OS << "Volatile ";
+
+      if (MRO.isLoad())
+        OS << "LD";
+      if (MRO.isStore())
+        OS << "ST";
+        
+      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
+      
+      if (!V)
+        OS << "<unknown>";
+      else if (!V->getName().empty())
+        OS << V->getName();
+      else if (isa<PseudoSourceValue>(V))
+        OS << *V;
+      else
+        OS << V;
+
+      OS << " + " << MRO.getOffset() << "]";
+    }
+  }
+
   OS << "\n";
 }
 
 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
-                                     const MRegisterInfo *RegInfo,
+                                     const TargetRegisterInfo *RegInfo,
                                      bool AddIfNotFound) {
   bool Found = false;
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
@@ -644,8 +689,8 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
         MO.setIsKill();
         Found = true;
         break;
-      } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
-                 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+      } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+                 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
                  RegInfo->isSuperRegister(IncomingReg, Reg) &&
                  MO.isKill())
         // A super-register kill already exists.
@@ -664,7 +709,7 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
 }
 
 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
-                                   const MRegisterInfo *RegInfo,
+                                   const TargetRegisterInfo *RegInfo,
                                    bool AddIfNotFound) {
   bool Found = false;
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
@@ -677,8 +722,8 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
         MO.setIsDead();
         Found = true;
         break;
-      } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
-                 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
+      } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
+                 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
                  RegInfo->isSuperRegister(IncomingReg, Reg) &&
                  MO.isDead())
         // There exists a super-register that's marked dead.
@@ -699,13 +744,13 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
 
 /// copyKillDeadInfo - copies killed/dead information from one instr to another
 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
-                                    const MRegisterInfo *RegInfo) {
+                                    const TargetRegisterInfo *RegInfo) {
   // If the instruction defines any virtual registers, update the VarInfo,
   // kill and dead information for the instruction.
   for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = OldMI->getOperand(i);
     if (MO.isRegister() && MO.getReg() &&
-        MRegisterInfo::isVirtualRegister(MO.getReg())) {
+        TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
       unsigned Reg = MO.getReg();
       if (MO.isDef()) {
         if (MO.isDead()) {