#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Support/LeakDetector.h"
#include "llvm/Support/Streams.h"
+#include <ostream>
using namespace llvm;
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
Op.IsKill = false;
Op.IsDead = false;
Op.contents.RegNo = *ImpDefs;
- Op.offset = 0;
Operands.push_back(Op);
}
if (TID->ImplicitUses)
Op.IsKill = false;
Op.IsDead = false;
Op.contents.RegNo = *ImpUses;
- Op.offset = 0;
Operands.push_back(Op);
}
}
/// implicit operands. It reserves space for number of operands specified by
/// TargetInstrDescriptor or the numOperands if it is not zero. (for
/// instructions with variable number of operands).
-MachineInstr::MachineInstr(const TargetInstrDescriptor &tid)
+MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
: TID(&tid), NumImplicitOps(0), parent(0) {
- if (TID->ImplicitDefs)
+ if (!NoImp && TID->ImplicitDefs)
for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
NumImplicitOps++;
- if (TID->ImplicitUses)
+ if (!NoImp && TID->ImplicitUses)
for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
NumImplicitOps++;
Operands.reserve(NumImplicitOps + TID->numOperands);
- addImplicitDefUseOperands();
+ if (!NoImp)
+ addImplicitDefUseOperands();
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
}
/// getOpcode - Returns the opcode of this MachineInstr.
///
-const int MachineInstr::getOpcode() const {
+int MachineInstr::getOpcode() const {
return TID->Opcode;
}
return false;
}
+/// getNumExplicitOperands - Returns the number of non-implicit operands.
+///
+unsigned MachineInstr::getNumExplicitOperands() const {
+ unsigned NumOperands = TID->numOperands;
+ if ((TID->Flags & M_VARIABLE_OPS) == 0)
+ return NumOperands;
+
+ for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
+ const MachineOperand &MO = getOperand(NumOperands);
+ if (!MO.isRegister() || !MO.isImplicit())
+ NumOperands++;
+ }
+ return NumOperands;
+}
+
/// isIdenticalTo - Return true if this operand is identical to the specified
/// operand.
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
}
}
-/// findRegisterUseOperand() - Returns the MachineOperand that is a use of
+/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
+/// the specific register or -1 if it is not found. It further tightening
+/// the search criteria to a use that kills the register if isKill is true.
+int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = getOperand(i);
+ if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
+ if (!isKill || MO.isKill())
+ return i;
+ }
+ return -1;
+}
+
+/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
/// the specific register or NULL if it is not found.
-MachineOperand *MachineInstr::findRegisterUseOperand(unsigned Reg) {
+MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
- if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
+ if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return &MO;
}
return NULL;
}
+
+/// findFirstPredOperandIdx() - Find the index of the first operand in the
+/// operand list that is used to represent the predicate. It returns -1 if
+/// none is found.
+int MachineInstr::findFirstPredOperandIdx() const {
+ const TargetInstrDescriptor *TID = getInstrDescriptor();
+ if (TID->Flags & M_PREDICABLE) {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+ if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+ return i;
+ }
+
+ return -1;
+}
+/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
+/// to two addr elimination.
+bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
+ const TargetInstrDescriptor *TID = getInstrDescriptor();
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO1 = getOperand(i);
+ if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
+ for (unsigned j = i+1; j < e; ++j) {
+ const MachineOperand &MO2 = getOperand(j);
+ if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
+ TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
///
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
+ if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
continue;
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
MachineOperand &MOp = getOperand(j);
}
}
+/// copyPredicates - Copies predicate operand(s) from MI.
+void MachineInstr::copyPredicates(const MachineInstr *MI) {
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_PREDICABLE) {
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ const MachineOperand &MO = MI->getOperand(i);
+ // Predicated operands must be last operands.
+ if (MO.isRegister())
+ addRegOperand(MO.getReg(), false);
+ else {
+ addImmOperand(MO.getImm());
+ }
+ }
+ }
+ }
+}
+
void MachineInstr::dump() const {
cerr << " " << *this;
}
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
+ if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
::print(getOperand(0), OS, TM);
+ if (getOperand(0).isDead())
+ OS << "<dead>";
OS << " = ";
++StartOp; // Don't print this operand again!
}
OS << " ";
::print(mop, OS, TM);
- if (mop.isReg()) {
+ if (mop.isRegister()) {
if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
OS << "<";
bool NeedComma = false;
OS << "\n";
}
-std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
+void MachineInstr::print(std::ostream &os) const {
// If the instruction is embedded into a basic block, we can find the target
// info for the instruction.
- if (const MachineBasicBlock *MBB = MI.getParent()) {
+ if (const MachineBasicBlock *MBB = getParent()) {
const MachineFunction *MF = MBB->getParent();
if (MF)
- MI.print(os, &MF->getTarget());
+ print(os, &MF->getTarget());
else
- MI.print(os, 0);
- return os;
+ print(os, 0);
}
// Otherwise, print it out in the "raw" format without symbolic register names
// and such.
- os << MI.getInstrDescriptor()->Name;
+ os << getInstrDescriptor()->Name;
- for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
- os << "\t" << MI.getOperand(i);
- if (MI.getOperand(i).isReg() && MI.getOperand(i).isDef())
+ for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
+ os << "\t" << getOperand(i);
+ if (getOperand(i).isRegister() && getOperand(i).isDef())
os << "<d>";
}
- return os << "\n";
+ os << "\n";
}
-std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
- switch (MO.getType()) {
- case MachineOperand::MO_Register:
- OutputReg(OS, MO.getReg());
+void MachineOperand::print(std::ostream &OS) const {
+ switch (getType()) {
+ case MO_Register:
+ OutputReg(OS, getReg());
break;
- case MachineOperand::MO_Immediate:
- OS << (long)MO.getImmedValue();
+ case MO_Immediate:
+ OS << (long)getImmedValue();
break;
- case MachineOperand::MO_MachineBasicBlock:
+ case MO_MachineBasicBlock:
OS << "<mbb:"
- << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
- << "@" << (void*)MO.getMachineBasicBlock() << ">";
+ << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
+ << "@" << (void*)getMachineBasicBlock() << ">";
break;
- case MachineOperand::MO_FrameIndex:
- OS << "<fi#" << MO.getFrameIndex() << ">";
+ case MO_FrameIndex:
+ OS << "<fi#" << getFrameIndex() << ">";
break;
- case MachineOperand::MO_ConstantPoolIndex:
- OS << "<cp#" << MO.getConstantPoolIndex() << ">";
+ case MO_ConstantPoolIndex:
+ OS << "<cp#" << getConstantPoolIndex() << ">";
break;
- case MachineOperand::MO_JumpTableIndex:
- OS << "<jt#" << MO.getJumpTableIndex() << ">";
+ case MO_JumpTableIndex:
+ OS << "<jt#" << getJumpTableIndex() << ">";
break;
- case MachineOperand::MO_GlobalAddress:
- OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
+ case MO_GlobalAddress:
+ OS << "<ga:" << ((Value*)getGlobal())->getName() << ">";
break;
- case MachineOperand::MO_ExternalSymbol:
- OS << "<es:" << MO.getSymbolName() << ">";
+ case MO_ExternalSymbol:
+ OS << "<es:" << getSymbolName() << ">";
break;
default:
assert(0 && "Unrecognized operand type");
break;
}
-
- return OS;
}
+
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