//===-- MachineInstr.cpp --------------------------------------------------===//
//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Methods common to all machine instructions.
+//
+// FIXME: Now that MachineInstrs have parent pointers, they should always
+// print themselves using their MachineFunction's TargetMachine.
+//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Value.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
-using std::cerr;
-
+#include "Support/LeakDetector.h"
+using namespace llvm;
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
-extern const TargetInstrDescriptor *TargetInstrDescriptors;
+namespace llvm {
+ extern const TargetInstrDescriptor *TargetInstrDescriptors;
+}
// Constructor for instructions with variable #operands
-MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
- : opCode(OpCode),
+MachineInstr::MachineInstr(short opcode, unsigned numOperands)
+ : Opcode(opcode),
+ numImplicitRefs(0),
operands(numOperands, MachineOperand()),
- numImplicitRefs(0)
-{
+ parent(0) {
+ // Make sure that we get added to a machine basicblock
+ LeakDetector::addGarbageObject(this);
}
/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
/// add* methods below to fill up the operands, instead of the Set methods.
/// Eventually, the "resizing" ctors will be phased out.
///
-MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
- bool XX, bool YY)
- : opCode(Opcode),
- numImplicitRefs(0)
-{
+MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
+ : Opcode(opcode), numImplicitRefs(0), parent(0) {
operands.reserve(numOperands);
+ // Make sure that we get added to a machine basicblock
+ LeakDetector::addGarbageObject(this);
}
/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
/// MachineInstr is created and added to the end of the specified basic block.
///
-MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
+MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
unsigned numOperands)
- : opCode(Opcode),
- numImplicitRefs(0)
-{
+ : Opcode(opcode), numImplicitRefs(0), parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
operands.reserve(numOperands);
+ // Make sure that we get added to a machine basicblock
+ LeakDetector::addGarbageObject(this);
MBB->push_back(this); // Add instruction to end of basic block!
}
-
-// OperandComplete - Return true if it's illegal to add a new operand
-bool MachineInstr::OperandsComplete() const
+MachineInstr::~MachineInstr()
{
- int NumOperands = TargetInstrDescriptors[opCode].numOperands;
+ LeakDetector::removeGarbageObject(this);
+}
+
+/// OperandComplete - Return true if it's illegal to add a new operand
+///
+bool MachineInstr::OperandsComplete() const {
+ int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
- return true; // Broken!
+ return true; // Broken: we have all the operands of this instruction!
return false;
}
-
-//
-// Support for replacing opcode and operands of a MachineInstr in place.
-// This only resets the size of the operand vector and initializes it.
-// The new operands must be set explicitly later.
-//
-void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
-{
+/// replace - Support for replacing opcode and operands of a MachineInstr in
+/// place. This only resets the size of the operand vector and initializes it.
+/// The new operands must be set explicitly later.
+///
+void MachineInstr::replace(short opcode, unsigned numOperands) {
assert(getNumImplicitRefs() == 0 &&
"This is probably broken because implicit refs are going to be lost.");
- opCode = Opcode;
+ Opcode = opcode;
operands.clear();
operands.resize(numOperands, MachineOperand());
}
-void
-MachineInstr::SetMachineOperandVal(unsigned i,
- MachineOperand::MachineOperandType opType,
- Value* V,
- bool isdef,
- bool isDefAndUse)
-{
+void MachineInstr::SetMachineOperandVal(unsigned i,
+ MachineOperand::MachineOperandType opTy,
+ Value* V) {
assert(i < operands.size()); // may be explicit or implicit op
- operands[i].opType = opType;
+ operands[i].opType = opTy;
operands[i].value = V;
operands[i].regNum = -1;
-
- if (isDefAndUse)
- operands[i].flags = MachineOperand::DEFUSEFLAG;
- else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
- operands[i].flags = MachineOperand::DEFONLYFLAG;
- else
- operands[i].flags = 0;
}
void
MachineInstr::SetMachineOperandConst(unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue)
-{
+ MachineOperand::MachineOperandType opTy,
+ int intValue) {
assert(i < getNumOperands()); // must be explicit op
- assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
+ assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
"immed. constant cannot be defined");
- operands[i].opType = operandType;
+ operands[i].opType = opTy;
operands[i].value = NULL;
operands[i].immedVal = intValue;
operands[i].regNum = -1;
operands[i].flags = 0;
}
-void
-MachineInstr::SetMachineOperandReg(unsigned i,
- int regNum,
- bool isdef) {
+void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
operands[i].opType = MachineOperand::MO_MachineRegister;
operands[i].value = NULL;
operands[i].regNum = regNum;
-
- if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
- operands[i].flags = MachineOperand::DEFONLYFLAG;
- else
- operands[i].flags = 0;
-
- insertUsedReg(regNum);
}
-void
-MachineInstr::SetRegForOperand(unsigned i, int regNum)
-{
+// Used only by the SPARC back-end.
+void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
operands[i].setRegForValue(regNum);
- insertUsedReg(regNum);
}
+// Used only by the SPARC back-end.
+void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
+ getImplicitOp(i).setRegForValue(regNum);
+}
-// Subsitute all occurrences of Value* oldVal with newVal in all operands
-// and all implicit refs. If defsOnly == true, substitute defs only.
+/// substituteValue - Substitute all occurrences of Value* oldVal with newVal
+/// in all operands and all implicit refs. If defsOnly == true, substitute defs
+/// only.
+///
+/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
+/// or make it a static function in that file.
+///
unsigned
-MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
+MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
+ bool defsOnly, bool notDefsAndUses,
+ bool& someArgsWereIgnored)
{
+ assert((!defsOnly || !notDefsAndUses) &&
+ "notDefsAndUses is irrelevant if defsOnly == true.");
+
unsigned numSubst = 0;
- // Subsitute operands
+ // Substitute operands
for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
if (*O == oldVal)
- if (!defsOnly || !O.isUseOnly())
+ if (!defsOnly ||
+ notDefsAndUses && (O.isDef() && !O.isUse()) ||
+ !notDefsAndUses && O.isDef())
{
O.getMachineOperand().value = newVal;
++numSubst;
}
+ else
+ someArgsWereIgnored = true;
- // Subsitute implicit refs
+ // Substitute implicit refs
for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
- if (!defsOnly || !getImplicitOp(i).opIsUse())
+ if (!defsOnly ||
+ notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
+ !notDefsAndUses && getImplicitOp(i).isDef())
{
getImplicitOp(i).value = newVal;
++numSubst;
}
+ else
+ someArgsWereIgnored = true;
return numSubst;
}
-
-void
-MachineInstr::dump() const
-{
- cerr << " " << *this;
+void MachineInstr::dump() const {
+ std::cerr << " " << *this;
}
-static inline std::ostream&
-OutputValue(std::ostream &os, const Value* val)
-{
+static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
os << "(val ";
+ os << (void*) val; // print address always
if (val && val->hasName())
- return os << val->getName() << ")";
- else
- return os << (void*) val << ")"; // print address only
+ os << " " << val->getName(); // print name also, if available
+ os << ")";
+ return os;
}
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
- if (MRI) {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
+ if (MRI)
os << "%" << MRI->get(RegNo).Name;
else
- os << "%reg" << RegNo;
+ os << "%mreg(" << RegNo << ")";
} else
- os << "%mreg(" << RegNo << ")";
+ os << "%reg" << RegNo;
}
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine &TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
bool CloseParen = true;
- if (MO.opHiBits32())
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
else
CloseParen = false;
OS << "==";
}
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_CCRegister:
OS << "%ccreg";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
}
break;
case MachineOperand::MO_MachineRegister:
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() &&
- (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
+ if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
OS << " ";
::print(mop, OS, TM);
- if (mop.opIsDefAndUse())
- OS << "<def&use>";
- else if (mop.opIsDefOnly())
- OS << "<def>";
+ if (mop.isDef())
+ if (mop.isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
- // code for printing implict references
+ // code for printing implicit references
if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: ";
for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
OS << "\t";
OutputValue(OS, getImplicitRef(i));
- if (getImplicitOp(i).opIsDefAndUse())
- OS << "<def&use>";
- else if (getImplicitOp(i).opIsDefOnly())
- OS << "<def>";
+ if (getImplicitOp(i).isDef())
+ if (getImplicitOp(i).isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
}
OS << "\n";
}
+namespace llvm {
+std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
+ // If the instruction is embedded into a basic block, we can find the target
+ // info for the instruction.
+ if (const MachineBasicBlock *MBB = MI.getParent()) {
+ const MachineFunction *MF = MBB->getParent();
+ MI.print(os, MF->getTarget());
+ return os;
+ }
-std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
-{
- os << TargetInstrDescriptors[MI.opCode].Name;
+ // Otherwise, print it out in the "raw" format without symbolic register names
+ // and such.
+ os << TargetInstrDescriptors[MI.getOpcode()].Name;
for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
- if (MI.getOperand(i).opIsDefOnly())
- os << "<d>";
- if (MI.getOperand(i).opIsDefAndUse())
- os << "<d&u>";
+ if (MI.getOperand(i).isDef())
+ if (MI.getOperand(i).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
}
- // code for printing implict references
+ // code for printing implicit references
unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) {
os << "\tImplicit: ";
for (unsigned z=0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z));
- if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
- if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
+ if (MI.getImplicitOp(z).isDef())
+ if (MI.getImplicitOp(z).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
os << "\t";
}
}
return os << "\n";
}
-std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
-{
- if (MO.opHiBits32())
+std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
switch (MO.getType())
{
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
if (MO.getVRegValue()) {
if (MO.hasAllocatedReg()) OS << "==";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
}
break;
case MachineOperand::MO_MachineRegister:
break;
}
- if (MO.flags &
- (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
- MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
+ if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")";
return OS;
}
+
+}
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