//===-- MachineInstr.cpp --------------------------------------------------===//
//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Methods common to all machine instructions.
+//
+// FIXME: Now that MachineInstrs have parent pointers, they should always
+// print themselves using their MachineFunction's TargetMachine.
+//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
+namespace llvm {
+
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class TargetInstrInfo.
extern const TargetInstrDescriptor *TargetInstrDescriptors;
// Constructor for instructions with variable #operands
-MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
- : opCode(OpCode),
- opCodeFlags(0),
+MachineInstr::MachineInstr(short opcode, unsigned numOperands)
+ : Opcode(opcode),
+ numImplicitRefs(0),
operands(numOperands, MachineOperand()),
- numImplicitRefs(0)
-{
+ parent(0) {
}
/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
/// add* methods below to fill up the operands, instead of the Set methods.
/// Eventually, the "resizing" ctors will be phased out.
///
-MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
- bool XX, bool YY)
- : opCode(Opcode),
- opCodeFlags(0),
- numImplicitRefs(0)
-{
+MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
+ : Opcode(opcode), numImplicitRefs(0), parent(0) {
operands.reserve(numOperands);
}
/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
/// MachineInstr is created and added to the end of the specified basic block.
///
-MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
+MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
unsigned numOperands)
- : opCode(Opcode),
- opCodeFlags(0),
- numImplicitRefs(0)
-{
+ : Opcode(opcode), numImplicitRefs(0), parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
operands.reserve(numOperands);
MBB->push_back(this); // Add instruction to end of basic block!
}
-
-// OperandComplete - Return true if it's illegal to add a new operand
-bool MachineInstr::OperandsComplete() const
-{
- int NumOperands = TargetInstrDescriptors[opCode].numOperands;
+/// OperandComplete - Return true if it's illegal to add a new operand
+///
+bool MachineInstr::OperandsComplete() const {
+ int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
return true; // Broken: we have all the operands of this instruction!
return false;
}
-
-//
-// Support for replacing opcode and operands of a MachineInstr in place.
-// This only resets the size of the operand vector and initializes it.
-// The new operands must be set explicitly later.
-//
-void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
-{
+/// replace - Support for replacing opcode and operands of a MachineInstr in
+/// place. This only resets the size of the operand vector and initializes it.
+/// The new operands must be set explicitly later.
+///
+void MachineInstr::replace(short opcode, unsigned numOperands) {
assert(getNumImplicitRefs() == 0 &&
"This is probably broken because implicit refs are going to be lost.");
- opCode = Opcode;
+ Opcode = opcode;
operands.clear();
operands.resize(numOperands, MachineOperand());
}
void
MachineInstr::SetMachineOperandConst(unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue)
-{
+ MachineOperand::MachineOperandType opTy,
+ int64_t intValue) {
assert(i < getNumOperands()); // must be explicit op
- assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
+ assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
"immed. constant cannot be defined");
- operands[i].opType = operandType;
+ operands[i].opType = opTy;
operands[i].value = NULL;
operands[i].immedVal = intValue;
operands[i].regNum = -1;
operands[i].regNum = regNum;
}
-void
-MachineInstr::SetRegForOperand(unsigned i, int regNum)
-{
+// Used only by the SPARC back-end.
+void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
operands[i].setRegForValue(regNum);
}
-void
-MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
-{
+// Used only by the SPARC back-end.
+void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
getImplicitOp(i).setRegForValue(regNum);
}
-
-// Substitute all occurrences of Value* oldVal with newVal in all operands
-// and all implicit refs.
-// If defsOnly == true, substitute defs only.
+/// substituteValue - Substitute all occurrences of Value* oldVal with newVal
+/// in all operands and all implicit refs. If defsOnly == true, substitute defs
+/// only.
+///
+/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
+/// or make it a static function in that file.
+///
unsigned
MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
bool defsOnly, bool notDefsAndUses,
for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
if (*O == oldVal)
if (!defsOnly ||
- notDefsAndUses && O.isDefOnly() ||
- !notDefsAndUses && !O.isUseOnly())
+ notDefsAndUses && (O.isDef() && !O.isUse()) ||
+ !notDefsAndUses && O.isDef())
{
O.getMachineOperand().value = newVal;
++numSubst;
for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
if (!defsOnly ||
- notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
- !notDefsAndUses && !getImplicitOp(i).opIsUse())
+ notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
+ !notDefsAndUses && getImplicitOp(i).isDef())
{
getImplicitOp(i).value = newVal;
++numSubst;
return numSubst;
}
-
-void
-MachineInstr::dump() const
-{
+void MachineInstr::dump() const {
std::cerr << " " << *this;
}
-static inline std::ostream&
-OutputValue(std::ostream &os, const Value* val)
-{
+static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
os << "(val ";
os << (void*) val; // print address always
if (val && val->hasName())
- os << " " << val->getName() << ")"; // print name also, if available
+ os << " " << val->getName(); // print name also, if available
+ os << ")";
return os;
}
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
if (MRI) {
- if (RegNo < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(RegNo))
os << "%" << MRI->get(RegNo).Name;
else
os << "%reg" << RegNo;
const TargetMachine &TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
bool CloseParen = true;
- if (MO.opHiBits32())
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
else
CloseParen = false;
OS << "==";
}
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_CCRegister:
OS << "%ccreg";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum(), MRI);
+ OutputReg(OS, MO.getReg(), MRI);
}
break;
case MachineOperand::MO_MachineRegister:
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() &&
- (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
- ::print(getOperand(0), OS, TM);
+ if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
+ llvm::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
}
if (i != StartOp)
OS << ",";
OS << " ";
- ::print(mop, OS, TM);
+ llvm::print(mop, OS, TM);
- if (mop.opIsDefAndUse())
- OS << "<def&use>";
- else if (mop.opIsDefOnly())
- OS << "<def>";
+ if (mop.isDef())
+ if (mop.isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
// code for printing implicit references
for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
OS << "\t";
OutputValue(OS, getImplicitRef(i));
- if (getImplicitOp(i).opIsDefAndUse())
- OS << "<def&use>";
- else if (getImplicitOp(i).opIsDefOnly())
- OS << "<def>";
+ if (getImplicitOp(i).isDef())
+ if (getImplicitOp(i).isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
}
OS << "\n";
}
-
-std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
-{
- os << TargetInstrDescriptors[MI.opCode].Name;
+std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) {
+ os << TargetInstrDescriptors[MI.getOpcode()].Name;
for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
- if (MI.getOperand(i).opIsDefOnly())
- os << "<d>";
- if (MI.getOperand(i).opIsDefAndUse())
- os << "<d&u>";
+ if (MI.getOperand(i).isDef())
+ if (MI.getOperand(i).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
}
// code for printing implicit references
os << "\tImplicit: ";
for (unsigned z=0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z));
- if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
- if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
+ if (MI.getImplicitOp(z).isDef())
+ if (MI.getImplicitOp(z).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
os << "\t";
}
}
return os << "\n";
}
-std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
-{
- if (MO.opHiBits32())
+std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
switch (MO.getType())
{
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
if (MO.getVRegValue()) {
if (MO.hasAllocatedReg()) OS << "==";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
- OutputReg(OS, MO.getAllocatedRegNum());
+ OutputReg(OS, MO.getReg());
}
break;
case MachineOperand::MO_MachineRegister:
return OS;
}
+
+} // End llvm namespace
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