//
//===----------------------------------------------------------------------===//
+#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Value.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetInstrDesc.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/LeakDetector.h"
#include "llvm/Support/Streams.h"
#include <ostream>
}
// Otherwise, add this operand to the head of the registers use/def list.
- MachineOperand *&Head = RegInfo->getRegUseDefListHead(getReg());
+ MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
- Contents.Reg.Next = Head;
+ // For SSA values, we prefer to keep the definition at the start of the list.
+ // we do this by skipping over the definition if it is at the head of the
+ // list.
+ if (*Head && (*Head)->isDef())
+ Head = &(*Head)->Contents.Reg.Next;
+
+ Contents.Reg.Next = *Head;
if (Contents.Reg.Next) {
assert(getReg() == Contents.Reg.Next->getReg() &&
"Different regs on the same list!");
Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
}
- Contents.Reg.Prev = &Head;
- Head = this;
+ Contents.Reg.Prev = Head;
+ *Head = this;
}
void MachineOperand::setReg(unsigned Reg) {
getSubReg() == Other.getSubReg();
case MachineOperand::MO_Immediate:
return getImm() == Other.getImm();
+ case MachineOperand::MO_FPImmediate:
+ return getFPImm() == Other.getFPImm();
case MachineOperand::MO_MachineBasicBlock:
return getMBB() == Other.getMBB();
case MachineOperand::MO_FrameIndex:
void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
switch (getType()) {
case MachineOperand::MO_Register:
- if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
+ if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
OS << "%reg" << getReg();
} else {
// If the instruction is embedded into a basic block, we can find the
NeedComma = true;
}
if (isKill() || isDead()) {
- if (NeedComma) OS << ",";
- if (isKill()) OS << "kill";
- if (isDead()) OS << "dead";
+ if (NeedComma) OS << ",";
+ if (isKill()) OS << "kill";
+ if (isDead()) OS << "dead";
}
OS << ">";
}
case MachineOperand::MO_Immediate:
OS << getImm();
break;
+ case MachineOperand::MO_FPImmediate:
+ if (getFPImm()->getType() == Type::FloatTy) {
+ OS << getFPImm()->getValueAPF().convertToFloat();
+ } else {
+ OS << getFPImm()->getValueAPF().convertToDouble();
+ }
+ break;
case MachineOperand::MO_MachineBasicBlock:
OS << "mbb<"
<< ((Value*)getMBB()->getBasicBlock())->getName()
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
-/// TargetInstrDescriptor or the numOperands if it is not zero. (for
+/// TargetInstrDesc or the numOperands if it is not zero. (for
/// instructions with variable number of operands).
-MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
+MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
: TID(&tid), NumImplicitOps(0), Parent(0) {
- if (!NoImp && TID->ImplicitDefs)
- for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+ if (!NoImp && TID->getImplicitDefs())
+ for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
NumImplicitOps++;
- if (!NoImp && TID->ImplicitUses)
- for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+ if (!NoImp && TID->getImplicitUses())
+ for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
NumImplicitOps++;
- Operands.reserve(NumImplicitOps + TID->numOperands);
+ Operands.reserve(NumImplicitOps + TID->getNumOperands());
if (!NoImp)
addImplicitDefUseOperands();
// Make sure that we get added to a machine basicblock
/// MachineInstr is created and added to the end of the specified basic block.
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
- const TargetInstrDescriptor &tid)
+ const TargetInstrDesc &tid)
: TID(&tid), NumImplicitOps(0), Parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
- for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+ for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
NumImplicitOps++;
if (TID->ImplicitUses)
- for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+ for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
NumImplicitOps++;
- Operands.reserve(NumImplicitOps + TID->numOperands);
+ Operands.reserve(NumImplicitOps + TID->getNumOperands());
addImplicitDefUseOperands();
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
- TID = MI.getInstrDescriptor();
+ TID = &MI.getDesc();
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
+ MemOperands = MI.MemOperands;
// Add operands
for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
/// OperandComplete - Return true if it's illegal to add a new operand
///
bool MachineInstr::OperandsComplete() const {
- unsigned short NumOperands = TID->numOperands;
- if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
- getNumOperands()-NumImplicitOps >= NumOperands)
+ unsigned short NumOperands = TID->getNumOperands();
+ if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
return true; // Broken: we have all the operands of this instruction!
return false;
}
/// getNumExplicitOperands - Returns the number of non-implicit operands.
///
unsigned MachineInstr::getNumExplicitOperands() const {
- unsigned NumOperands = TID->numOperands;
- if ((TID->Flags & M_VARIABLE_OPS) == 0)
+ unsigned NumOperands = TID->getNumOperands();
+ if (!TID->isVariadic())
return NumOperands;
for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
}
+/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
+///
+bool MachineInstr::isDebugLabel() const {
+ return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
+}
+
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
/// the specific register or -1 if it is not found. It further tightening
/// the search criteria to a use that kills the register if isKill is true.
-int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
+int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
+ const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
+ if (!MO.isRegister() || !MO.isUse())
+ continue;
+ unsigned MOReg = MO.getReg();
+ if (!MOReg)
+ continue;
+ if (MOReg == Reg ||
+ (TRI &&
+ TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TRI->isSubRegister(MOReg, Reg)))
if (!isKill || MO.isKill())
return i;
}
return -1;
}
-/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
-/// the specific register or NULL if it is not found.
-MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
+/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
+/// the specified register or -1 if it is not found. If isDead is true, defs
+/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
+/// also checks if there is a def of a super-register.
+int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
+ const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
- MachineOperand &MO = getOperand(i);
- if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
- return &MO;
+ const MachineOperand &MO = getOperand(i);
+ if (!MO.isRegister() || !MO.isDef())
+ continue;
+ unsigned MOReg = MO.getReg();
+ if (MOReg == Reg ||
+ (TRI &&
+ TargetRegisterInfo::isPhysicalRegister(MOReg) &&
+ TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ TRI->isSubRegister(MOReg, Reg)))
+ if (!isDead || MO.isDead())
+ return i;
}
- return NULL;
+ return -1;
}
/// findFirstPredOperandIdx() - Find the index of the first operand in the
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
- const TargetInstrDescriptor *TID = getInstrDescriptor();
- if (TID->Flags & M_PREDICABLE) {
+ const TargetInstrDesc &TID = getDesc();
+ if (TID.isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
+ if (TID.OpInfo[i].isPredicate())
return i;
}
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
- const TargetInstrDescriptor *TID = getInstrDescriptor();
+ const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
for (unsigned j = i+1; j < e; ++j) {
const MachineOperand &MO2 = getOperand(j);
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
- TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
+ TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
return true;
}
}
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
- const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
- if (TID->Flags & M_PREDICABLE) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
- // Predicated operands must be last operands.
- addOperand(MI->getOperand(i));
- }
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isPredicable())
+ return;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if (TID.OpInfo[i].isPredicate()) {
+ // Predicated operands must be last operands.
+ addOperand(MI->getOperand(i));
}
}
}
+/// isSafeToMove - Return true if it is safe to this instruction. If SawStore is
+/// set to true, it means that there is a store (or call) between the
+/// instruction's location and its intended destination.
+bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
+ // Ignore stuff that we obviously can't move.
+ if (TID->mayStore() || TID->isCall()) {
+ SawStore = true;
+ return false;
+ }
+ if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
+ return false;
+
+ // See if this instruction does a load. If so, we have to guarantee that the
+ // loaded value doesn't change between the load and the its intended
+ // destination. The check for isInvariantLoad gives the targe the chance to
+ // classify the load as always returning a constant, e.g. a constant pool
+ // load.
+ if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
+ // Otherwise, this is a real load. If there is a store between the load and
+ // end of block, we can't sink the load.
+ //
+ // FIXME: we can't do this transformation until we know that the load is
+ // not volatile, and machineinstrs don't keep this info. :(
+ //
+ //if (SawStore)
+ return false;
+ }
+ return true;
+}
+
void MachineInstr::dump() const {
cerr << " " << *this;
}
++StartOp; // Don't print this operand again!
}
- OS << getInstrDescriptor()->Name;
+ OS << getDesc().getName();
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
if (i != StartOp)
getOperand(i).print(OS, TM);
}
+ if (getNumMemOperands() > 0) {
+ OS << ", Mem:";
+ for (unsigned i = 0; i < getNumMemOperands(); i++) {
+ const MachineMemOperand &MRO = getMemOperand(i);
+ const Value *V = MRO.getValue();
+
+ assert((MRO.isLoad() || MRO.isStore()) &&
+ "SV has to be a load, store or both.");
+
+ if (MRO.isVolatile())
+ OS << "Volatile ";
+
+ if (MRO.isLoad())
+ OS << "LD";
+ if (MRO.isStore())
+ OS << "ST";
+
+ OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
+
+ if (!V)
+ OS << "<unknown>";
+ else if (!V->getName().empty())
+ OS << V->getName();
+ else if (isa<PseudoSourceValue>(V))
+ OS << *V;
+ else
+ OS << V;
+
+ OS << " + " << MRO.getOffset() << "]";
+ }
+ }
+
OS << "\n";
}
+bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo,
+ bool AddIfNotFound) {
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
+ bool Found = false;
+ SmallVector<unsigned,4> DeadOps;
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = getOperand(i);
+ if (!MO.isRegister() || !MO.isUse())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+
+ if (Reg == IncomingReg) {
+ if (!Found) // One kill of reg per instruction.
+ MO.setIsKill();
+ Found = true;
+ } else if (isPhysReg && MO.isKill() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ // A super-register kill already exists.
+ if (RegInfo->isSuperRegister(IncomingReg, Reg))
+ Found = true;
+ else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ DeadOps.push_back(i);
+ }
+ }
+
+ // Trim unneeded kill operands.
+ while (!DeadOps.empty()) {
+ unsigned OpIdx = DeadOps.back();
+ if (getOperand(OpIdx).isImplicit())
+ RemoveOperand(OpIdx);
+ else
+ getOperand(OpIdx).setIsKill(false);
+ DeadOps.pop_back();
+ }
+
+ // If not found, this means an alias of one of the operands is killed. Add a
+ // new implicit operand if required.
+ if (!Found && AddIfNotFound) {
+ addOperand(MachineOperand::CreateReg(IncomingReg,
+ false /*IsDef*/,
+ true /*IsImp*/,
+ true /*IsKill*/));
+ return true;
+ }
+ return Found;
+}
+
+bool MachineInstr::addRegisterDead(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo,
+ bool AddIfNotFound) {
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
+ bool Found = false;
+ SmallVector<unsigned,4> DeadOps;
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = getOperand(i);
+ if (!MO.isRegister() || !MO.isDef())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (Reg == IncomingReg) {
+ MO.setIsDead();
+ Found = true;
+ } else if (isPhysReg && MO.isDead() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ // There exists a super-register that's marked dead.
+ if (RegInfo->isSuperRegister(IncomingReg, Reg))
+ Found = true;
+ else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ DeadOps.push_back(i);
+ }
+ }
+
+ // Trim unneeded dead operands.
+ while (!DeadOps.empty()) {
+ unsigned OpIdx = DeadOps.back();
+ if (getOperand(OpIdx).isImplicit())
+ RemoveOperand(OpIdx);
+ else
+ getOperand(OpIdx).setIsDead(false);
+ DeadOps.pop_back();
+ }
+
+ // If not found, this means an alias of one of the operand is dead. Add a
+ // new implicit operand.
+ if (!Found && AddIfNotFound) {
+ addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
+ true/*IsImp*/,false/*IsKill*/,
+ true/*IsDead*/));
+ return true;
+ }
+ return Found;
+}
+
+/// copyKillDeadInfo - copies killed/dead information from one instr to another
+void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
+ const TargetRegisterInfo *RegInfo) {
+ // If the instruction defines any virtual registers, update the VarInfo,
+ // kill and dead information for the instruction.
+ for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = OldMI->getOperand(i);
+ if (MO.isRegister() && MO.getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+ unsigned Reg = MO.getReg();
+ if (MO.isDef()) {
+ if (MO.isDead()) {
+ MO.setIsDead(false);
+ addRegisterDead(Reg, RegInfo);
+ }
+ }
+ if (MO.isKill()) {
+ MO.setIsKill(false);
+ addRegisterKilled(Reg, RegInfo);
+ }
+ }
+ }
+}
projects / oota-llvm.git / blobdiff