#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetInstrDesc.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Support/LeakDetector.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Streams.h"
#include <ostream>
using namespace llvm;
}
}
+//===----------------------------------------------------------------------===//
+// MachineMemOperand Implementation
+//===----------------------------------------------------------------------===//
+
+MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
+ int64_t o, uint64_t s, unsigned int a)
+ : Offset(o), Size(s), V(v),
+ Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
+ assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
+}
+
//===----------------------------------------------------------------------===//
// MachineInstr Implementation
//===----------------------------------------------------------------------===//
/// TID NULL and no operands.
MachineInstr::MachineInstr()
: TID(0), NumImplicitOps(0), Parent(0) {
- // Make sure that we get added to a machine basicblock
- LeakDetector::addGarbageObject(this);
}
void MachineInstr::addImplicitDefUseOperands() {
Operands.reserve(NumImplicitOps + TID->getNumOperands());
if (!NoImp)
addImplicitDefUseOperands();
- // Make sure that we get added to a machine basicblock
- LeakDetector::addGarbageObject(this);
}
/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
NumImplicitOps++;
Operands.reserve(NumImplicitOps + TID->getNumOperands());
addImplicitDefUseOperands();
- // Make sure that we get added to a machine basicblock
- LeakDetector::addGarbageObject(this);
MBB->push_back(this); // Add instruction to end of basic block!
}
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
-MachineInstr::MachineInstr(const MachineInstr &MI) {
+MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) {
TID = &MI.getDesc();
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
- MemOperands = MI.MemOperands;
// Add operands
for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
Operands.back().ParentMI = this;
}
- // Set parent, next, and prev to null
+ // Add memory operands.
+ for (alist<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
+ j = MI.memoperands_end(); i != j; ++i)
+ addMemOperand(MF, *i);
+
+ // Set parent to null.
Parent = 0;
- Prev = 0;
- Next = 0;
}
-
MachineInstr::~MachineInstr() {
- LeakDetector::removeGarbageObject(this);
+ assert(MemOperands.empty() &&
+ "MachineInstr being deleted with live memoperands!");
#ifndef NDEBUG
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
/// return null.
MachineRegisterInfo *MachineInstr::getRegInfo() {
if (MachineBasicBlock *MBB = getParent())
- if (MachineFunction *MF = MBB->getParent())
- return &MF->getRegInfo();
+ return &MBB->getParent()->getRegInfo();
return 0;
}
}
}
+/// addMemOperand - Add a MachineMemOperand to the machine instruction,
+/// referencing arbitrary storage.
+void MachineInstr::addMemOperand(MachineFunction &MF,
+ const MachineMemOperand &MO) {
+ MemOperands.push_back(MF.CreateMachineMemOperand(MO));
+}
+
+/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
+void MachineInstr::clearMemOperands(MachineFunction &MF) {
+ while (!MemOperands.empty())
+ MF.DeleteMachineMemOperand(MemOperands.remove(MemOperands.begin()));
+}
+
/// removeFromParent - This method unlinks 'this' from the containing basic
/// block, and returns it, but does not delete it.
}
+/// eraseFromParent - This method unlinks 'this' from the containing basic
+/// block, and deletes it.
+void MachineInstr::eraseFromParent() {
+ assert(getParent() && "Not embedded in a basic block!");
+ getParent()->erase(this);
+}
+
+
/// OperandComplete - Return true if it's illegal to add a new operand
///
bool MachineInstr::OperandsComplete() const {
}
}
-/// isSafeToMove - Return true if it is safe to this instruction. If SawStore is
-/// set to true, it means that there is a store (or call) between the
-/// instruction's location and its intended destination.
+/// isSafeToMove - Return true if it is safe to move this instruction. If
+/// SawStore is set to true, it means that there is a store (or call) between
+/// the instruction's location and its intended destination.
bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
// Ignore stuff that we obviously can't move.
if (TID->mayStore() || TID->isCall()) {
getOperand(i).print(OS, TM);
}
- if (getNumMemOperands() > 0) {
+ if (!memoperands_empty()) {
OS << ", Mem:";
- for (unsigned i = 0; i < getNumMemOperands(); i++) {
- const MachineMemOperand &MRO = getMemOperand(i);
+ for (alist<MachineMemOperand>::const_iterator i = memoperands_begin(),
+ e = memoperands_end(); i != e; ++i) {
+ const MachineMemOperand &MRO = *i;
const Value *V = MRO.getValue();
assert((MRO.isLoad() || MRO.isStore()) &&
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
- bool Found = false;
+ bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
continue;
if (Reg == IncomingReg) {
- if (!Found) // One kill of reg per instruction.
- MO.setIsKill();
- Found = true;
- } else if (isPhysReg && MO.isKill() &&
- TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ MO.setIsKill();
+ return true;
+ }
+ if (hasAliases && MO.isKill() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
// A super-register kill already exists.
if (RegInfo->isSuperRegister(IncomingReg, Reg))
- Found = true;
- else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ return true;
+ if (RegInfo->isSubRegister(IncomingReg, Reg))
DeadOps.push_back(i);
}
}
// If not found, this means an alias of one of the operands is killed. Add a
// new implicit operand if required.
- if (!Found && AddIfNotFound) {
+ if (AddIfNotFound) {
addOperand(MachineOperand::CreateReg(IncomingReg,
false /*IsDef*/,
true /*IsImp*/,
true /*IsKill*/));
return true;
}
- return Found;
+ return false;
}
bool MachineInstr::addRegisterDead(unsigned IncomingReg,
bool AddIfNotFound) {
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
- bool Found = false;
SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
unsigned Reg = MO.getReg();
if (Reg == IncomingReg) {
MO.setIsDead();
- Found = true;
- } else if (hasAliases && MO.isDead() &&
- TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ return true;
+ }
+ if (hasAliases && MO.isDead() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
// There exists a super-register that's marked dead.
if (RegInfo->isSuperRegister(IncomingReg, Reg))
- Found = true;
- else if (RegInfo->isSubRegister(IncomingReg, Reg))
+ return true;
+ if (RegInfo->isSubRegister(IncomingReg, Reg))
DeadOps.push_back(i);
}
}
// If not found, this means an alias of one of the operand is dead. Add a
// new implicit operand.
- if (!Found && AddIfNotFound) {
+ if (AddIfNotFound) {
addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
true/*IsImp*/,false/*IsKill*/,
true/*IsDead*/));
return true;
}
- return Found;
-}
-
-/// copyKillDeadInfo - copies killed/dead information from one instr to another
-void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
- const TargetRegisterInfo *RegInfo) {
- // If the instruction defines any virtual registers, update the VarInfo,
- // kill and dead information for the instruction.
- for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = OldMI->getOperand(i);
- if (MO.isRegister() && MO.getReg() &&
- TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
- unsigned Reg = MO.getReg();
- if (MO.isDef()) {
- if (MO.isDead()) {
- MO.setIsDead(false);
- addRegisterDead(Reg, RegInfo);
- }
- }
- if (MO.isKill()) {
- MO.setIsKill(false);
- addRegisterKilled(Reg, RegInfo);
- }
- }
- }
+ return false;
}
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