#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
public:
static char ID; // Pass identification
- MachineSinking() : MachineFunctionPass((intptr_t)&ID) {}
+ MachineSinking() : MachineFunctionPass(&ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
bool SinkInstruction(MachineInstr *MI, bool &SawStore);
bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const;
};
-
- char MachineSinking::ID = 0;
- RegisterPass<MachineSinking> X("machine-sink", "Machine code sinking");
} // end anonymous namespace
+
+char MachineSinking::ID = 0;
+static RegisterPass<MachineSinking>
+X("machine-sink", "Machine code sinking");
FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
/// occur in blocks dominated by the specified block.
bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
MachineBasicBlock *MBB) const {
- assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
+ assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
+ "Only makes sense for vregs");
for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
E = RegInfo->reg_end(); I != E; ++I) {
if (I.getOperand().isDef()) continue; // ignore def.
}
bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
- bool MadeChange = false;
-
// Can't sink anything out of a block that has less than two successors.
- if (MBB.succ_size() <= 1) return false;
-
+ if (MBB.succ_size() <= 1 || MBB.empty()) return false;
+
+ bool MadeChange = false;
+
// Walk the basic block bottom-up. Remember if we saw a store.
- bool SawStore = false;
- for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ){
- MachineBasicBlock::iterator LastIt = I;
- if (SinkInstruction(--I, SawStore)) {
- I = LastIt;
- ++NumSunk;
- }
- }
+ MachineBasicBlock::iterator I = MBB.end();
+ --I;
+ bool ProcessedBegin, SawStore = false;
+ do {
+ MachineInstr *MI = I; // The instruction to sink.
+
+ // Predecrement I (if it's not begin) so that it isn't invalidated by
+ // sinking.
+ ProcessedBegin = I == MBB.begin();
+ if (!ProcessedBegin)
+ --I;
+
+ if (SinkInstruction(MI, SawStore))
+ ++NumSunk, MadeChange = true;
+
+ // If we just processed the first instruction in the block, we're done.
+ } while (!ProcessedBegin);
return MadeChange;
}
/// SinkInstruction - Determine whether it is safe to sink the specified machine
/// instruction out of its current block into a successor.
bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
- const TargetInstrDesc &TID = MI->getDesc();
-
- // Ignore stuff that we obviously can't sink.
- if (TID.mayStore() || TID.isCall()) {
- SawStore = true;
- return false;
- }
- if (TID.isReturn() || TID.isBranch() || TID.hasUnmodeledSideEffects())
+ // Check if it's safe to move the instruction.
+ if (!MI->isSafeToMove(TII, SawStore))
return false;
-
- // See if this instruction does a load. If so, we have to guarantee that the
- // loaded value doesn't change between the load and the end of block. The
- // check for isInvariantLoad gives the targe the chance to classify the load
- // as always returning a constant, e.g. a constant pool load.
- if (TID.mayLoad() && !TII->isInvariantLoad(MI)) {
- // Otherwise, this is a real load. If there is a store between the load and
- // end of block, we can't sink the load.
- //
- // FIXME: we can't do this transformation until we know that the load is
- // not volatile, and machineinstrs don't keep this info. :(
- //
- //if (SawStore)
- return false;
- }
// FIXME: This should include support for sinking instructions within the
// block they are currently in to shorten the live ranges. We often get
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
- if (MRegisterInfo::isPhysicalRegister(Reg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// If this is a physical register use, we can't move it. If it is a def,
// we can move it, but only if the def is dead.
if (MO.isUse() || !MO.isDead())
} else {
// Virtual register uses are always safe to sink.
if (MO.isUse()) continue;
+
+ // If it's not safe to move defs of the register class, then abort.
+ if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg)))
+ return false;
// FIXME: This picks a successor to sink into based on having one
// successor that dominates all the uses. However, there are cases where
// If there are no outputs, it must have side-effects.
if (SuccToSinkTo == 0)
return false;
+
+ // It's not safe to sink instructions to EH landing pad. Control flow into
+ // landing pad is implicitly defined.
+ if (SuccToSinkTo->isLandingPad())
+ return false;
+
+ // If is not possible to sink an instruction into its own block. This can
+ // happen with loops.
+ if (MI->getParent() == SuccToSinkTo)
+ return false;
DEBUG(cerr << "Sink instr " << *MI);
DEBUG(cerr << "to block " << *SuccToSinkTo);
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