Correct some thinkos in the expansion of ADD/SUB

[oota-llvm.git] / lib / CodeGen / MachineSink.cpp

diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp
index 29b0b3f7743dd4090a1e42dd2759255dbe5c9d1b..0f608d637c537a7fd4c1afab8e111c33ff441393 100644 (file)
--- a/lib/CodeGen/MachineSink.cpp
+++ b/lib/CodeGen/MachineSink.cpp
@@ -15,7 +15,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
@@ -36,7 +36,7 @@ namespace {
 
   public:
     static char ID; // Pass identification
-    MachineSinking() : MachineFunctionPass((intptr_t)&ID) {}
+    MachineSinking() : MachineFunctionPass(&ID) {}
     
     virtual bool runOnMachineFunction(MachineFunction &MF);
     
@@ -50,10 +50,11 @@ namespace {
     bool SinkInstruction(MachineInstr *MI, bool &SawStore);
     bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const;
   };
-  
-  char MachineSinking::ID = 0;
-  RegisterPass<MachineSinking> X("machine-sink", "Machine code sinking");
 } // end anonymous namespace
+  
+char MachineSinking::ID = 0;
+static RegisterPass<MachineSinking>
+X("machine-sink", "Machine code sinking");
 
 FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
 
@@ -61,7 +62,8 @@ FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
 /// occur in blocks dominated by the specified block.
 bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, 
                                              MachineBasicBlock *MBB) const {
-  assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
+  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
+         "Only makes sense for vregs");
   for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
        E = RegInfo->reg_end(); I != E; ++I) {
     if (I.getOperand().isDef()) continue;  // ignore def.
@@ -131,30 +133,9 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
 /// SinkInstruction - Determine whether it is safe to sink the specified machine
 /// instruction out of its current block into a successor.
 bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
-  const TargetInstrDesc &TID = MI->getDesc();
-  
-  // Ignore stuff that we obviously can't sink.
-  if (TID.mayStore() || TID.isCall()) {
-    SawStore = true;
-    return false;
-  }
-  if (TID.isReturn() || TID.isBranch() || TID.hasUnmodeledSideEffects())
-    return false;
-
-  // See if this instruction does a load.  If so, we have to guarantee that the
-  // loaded value doesn't change between the load and the end of block.  The
-  // check for isInvariantLoad gives the targe the chance to classify the load
-  // as always returning a constant, e.g. a constant pool load.
-  if (TID.mayLoad() && !TII->isInvariantLoad(MI)) {
-    // Otherwise, this is a real load.  If there is a store between the load and
-    // end of block, we can't sink the load.
-    //
-    // FIXME: we can't do this transformation until we know that the load is
-    // not volatile, and machineinstrs don't keep this info. :(
-    //
-    //if (SawStore) 
+  // Check if it's safe to move the instruction.
+  if (!MI->isSafeToMove(TII, SawStore))
     return false;
-  }
   
   // FIXME: This should include support for sinking instructions within the
   // block they are currently in to shorten the live ranges.  We often get
@@ -179,7 +160,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
     
-    if (MRegisterInfo::isPhysicalRegister(Reg)) {
+    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
       // If this is a physical register use, we can't move it.  If it is a def,
       // we can move it, but only if the def is dead.
       if (MO.isUse() || !MO.isDead())