Pass alignment on ByVal parameters, from FE, all

[oota-llvm.git] / lib / CodeGen / MachineSink.cpp

diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp
index b83d844a16234e665bd6948f2e2f075e6e8a745c..db2fab04f00d22afe8215c3cdde4fde1c458b700 100644 (file)
--- a/lib/CodeGen/MachineSink.cpp
+++ b/lib/CodeGen/MachineSink.cpp
@@ -15,7 +15,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
@@ -47,7 +47,7 @@ namespace {
     }
   private:
     bool ProcessBlock(MachineBasicBlock &MBB);
-    bool SinkInstruction(MachineInstr *MI);
+    bool SinkInstruction(MachineInstr *MI, bool &SawStore);
     bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const;
   };
   
@@ -61,7 +61,8 @@ FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
 /// occur in blocks dominated by the specified block.
 bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, 
                                              MachineBasicBlock *MBB) const {
-  assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
+  assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
+         "Only makes sense for vregs");
   for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
        E = RegInfo->reg_end(); I != E; ++I) {
     if (I.getOperand().isDef()) continue;  // ignore def.
@@ -115,10 +116,11 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
   // Can't sink anything out of a block that has less than two successors.
   if (MBB.succ_size() <= 1) return false;
   
-  // Walk the basic block bottom-up
+  // Walk the basic block bottom-up.  Remember if we saw a store.
+  bool SawStore = false;
   for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ){
     MachineBasicBlock::iterator LastIt = I;
-    if (SinkInstruction(--I)) {
+    if (SinkInstruction(--I, SawStore)) {
       I = LastIt;
       ++NumSunk;
     }
@@ -129,23 +131,31 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
 
 /// SinkInstruction - Determine whether it is safe to sink the specified machine
 /// instruction out of its current block into a successor.
-bool MachineSinking::SinkInstruction(MachineInstr *MI) {
+bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
   const TargetInstrDesc &TID = MI->getDesc();
   
   // Ignore stuff that we obviously can't sink.
-  if (TID.mayStore() || TID.isCall() || TID.isReturn() || TID.isBranch())
+  if (TID.mayStore() || TID.isCall()) {
+    SawStore = true;
     return false;
-
-  if (TID.mayLoad())
+  }
+  if (TID.isReturn() || TID.isBranch() || TID.hasUnmodeledSideEffects())
     return false;
-  
-  // Don't sink things with side-effects we don't understand.
-  if (TII->hasUnmodelledSideEffects(MI))
+
+  // See if this instruction does a load.  If so, we have to guarantee that the
+  // loaded value doesn't change between the load and the end of block.  The
+  // check for isInvariantLoad gives the targe the chance to classify the load
+  // as always returning a constant, e.g. a constant pool load.
+  if (TID.mayLoad() && !TII->isInvariantLoad(MI)) {
+    // Otherwise, this is a real load.  If there is a store between the load and
+    // end of block, we can't sink the load.
+    //
+    // FIXME: we can't do this transformation until we know that the load is
+    // not volatile, and machineinstrs don't keep this info. :(
+    //
+    //if (SawStore) 
     return false;
-  
-  // FIXME: we should be able to sink loads with no other side effects if there
-  // is nothing that can change memory from here until the end of block.  This
-  // is a trivial form of alias analysis.
+  }
   
   // FIXME: This should include support for sinking instructions within the
   // block they are currently in to shorten the live ranges.  We often get
@@ -170,7 +180,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI) {
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
     
-    if (MRegisterInfo::isPhysicalRegister(Reg)) {
+    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
       // If this is a physical register use, we can't move it.  If it is a def,
       // we can move it, but only if the def is dead.
       if (MO.isUse() || !MO.isDead())