initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
}
- void getAnalysisUsage(AnalysisUsage &AU) const {
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
- bool runOnMachineFunction(MachineFunction &MF) {
+ bool runOnMachineFunction(MachineFunction &MF) override {
MF.verify(this, Banner);
return false;
}
raw_ostream *OutFile = 0;
if (OutFileName) {
std::string ErrorInfo;
- OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, sys::fs::F_Append);
+ OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
+ sys::fs::F_Append | sys::fs::F_Text);
if (!ErrorInfo.empty()) {
errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
exit(1);
void MachineVerifier::report(const char *msg, const MachineFunction *MF,
const LiveInterval &LI) {
report(msg, MF);
- *OS << "- interval: ";
- if (TargetRegisterInfo::isVirtualRegister(LI.reg))
- *OS << PrintReg(LI.reg, TRI);
- else
- *OS << PrintRegUnit(LI.reg, TRI);
- *OS << ' ' << LI << '\n';
+ *OS << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
const LiveInterval &LI) {
report(msg, MBB);
- *OS << "- interval: ";
- if (TargetRegisterInfo::isVirtualRegister(LI.reg))
- *OS << PrintReg(LI.reg, TRI);
- else
- *OS << PrintRegUnit(LI.reg, TRI);
- *OS << ' ' << LI << '\n';
+ *OS << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
*OS << MCID.getNumOperands() << " operands expected, but "
- << MI->getNumExplicitOperands() << " given.\n";
+ << MI->getNumOperands() << " given.\n";
}
// Check the tied operands.
// Check the cached regunit intervals.
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
- if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) {
- LiveQueryResult LRQ = LI->Query(UseIdx);
+ if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
+ LiveQueryResult LRQ = LR->Query(UseIdx);
if (!LRQ.valueIn()) {
report("No live segment at use", MO, MONum);
*OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
- << ' ' << *LI << '\n';
+ << ' ' << *LR << '\n';
}
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
- *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n';
+ *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
}
}
}
// Verify SSA form.
if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
- llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
+ std::next(MRI->def_begin(Reg)) != MRI->def_end())
report("Multiple virtual register defs in SSA form", MO, MONum);
// Check LiveInts for a live segment, but only for virtual registers.
report("No live segment at def", MO, MONum);
*OS << DefIdx << " is not live in " << LI << '\n';
}
+ // Check that, if the dead def flag is present, LiveInts agree.
+ if (MO->isDead()) {
+ LiveQueryResult LRQ = LI.Query(DefIdx);
+ if (!LRQ.isDeadDef()) {
+ report("Live range continues after dead def flag", MO, MONum);
+ *OS << "Live range: " << LI << '\n';
+ }
+ }
} else {
report("Virtual register has no Live interval", MO, MONum);
}
// Verify all the cached regunit intervals.
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
- if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
- verifyLiveInterval(*LI);
+ if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
+ verifyLiveRange(*LR, i);
}
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
// A live segment can end with either a redefinition, a kill flag on a
// use, or a dead flag on a def.
bool hasRead = false;
- bool hasDeadDef = false;
for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || MOI->getReg() != Reg)
continue;
if (MOI->readsReg())
hasRead = true;
- if (MOI->isDef() && MOI->isDead())
- hasDeadDef = true;
}
-
- if (S.end.isDead()) {
- if (!hasDeadDef) {
- report("Instruction doesn't have a dead def operand", MI);
- *OS << S << " in " << LR << '\n';
- }
- } else {
+ if (!S.end.isDead()) {
if (!hasRead) {
report("Instruction ending live segment doesn't read the register", MI);
*OS << S << " in " << LR << '\n';