80 column and trailing whitespace cleanup

[oota-llvm.git] / lib / CodeGen / OptimizeExts.cpp

diff --git a/lib/CodeGen/OptimizeExts.cpp b/lib/CodeGen/OptimizeExts.cpp
index 38f3cf7e41c1a07680d233b880416ac53af4e6e0..dcdc243e5db342d4908f712387dbebcb15c07508 100644 (file)
--- a/lib/CodeGen/OptimizeExts.cpp
+++ b/lib/CodeGen/OptimizeExts.cpp
@@ -128,12 +128,12 @@ bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
       //
       //    %reg1025 = <sext> %reg1024
       //     ...
-      //    %reg1027 = EXTRACT_SUBREG %reg1025, 4
+      //    %reg1027 = COPY %reg1025:4
       //    %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
       //
       // The problem here is that SUBREG_TO_REG is there to assert that an
       // implicit zext occurs. It doesn't insert a zext instruction. If we allow
-      // the EXTRACT_SUBREG here, it will give us the value after the <sext>,
+      // the COPY here, it will give us the value after the <sext>,
       // not the original value of %reg1024 before <sext>.
       if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
         continue;
@@ -185,8 +185,8 @@ bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
           continue;
         unsigned NewVR = MRI->createVirtualRegister(RC);
         BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
-                TII->get(TargetOpcode::EXTRACT_SUBREG), NewVR)
-          .addReg(DstReg).addImm(SubIdx);
+                TII->get(TargetOpcode::COPY), NewVR)
+          .addReg(DstReg, 0, SubIdx);
         UseMO->setReg(NewVR);
         ++NumReuse;
         Changed = true;