void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
+ AU.addPreserved<SlotIndexes>();
AU.addPreserved<LiveIntervals>();
AU.addPreserved<MachineDominatorTree>();
AU.addPreserved<MachineLoopInfo>();
// Clean up the lowered PHI instructions.
for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
I != E; ++I) {
- if (LIS)
- LIS->RemoveMachineInstrFromMaps(I->first);
+ if (LIS)
+ LIS->RemoveMachineInstrFromMaps(I->first);
MF.DeleteMachineInstr(I->first);
}
ImpDefs.clear();
VRegPHIUseCount.clear();
- if (LIS)
- MF.verify(this, "After PHI elimination");
-
return Changed;
}
// Update LiveIntervals for the new copy or implicit def.
if (LIS) {
MachineInstr *NewInstr = prior(AfterPHIsIt);
- LIS->InsertMachineInstrInMaps(NewInstr);
+ SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
- SlotIndex DestCopyIndex = LIS->getInstructionIndex(NewInstr);
if (IncomingReg) {
// Add the region from the beginning of MBB to the copy instruction to
// IncomingReg's live interval.
IncomingVNI));
}
- LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg);
- if (NewInstr->getOperand(0).isDead()) {
+ LiveInterval &DestLI = LIS->getInterval(DestReg);
+ assert(DestLI.begin() != DestLI.end() &&
+ "PHIs should have nonempty LiveIntervals.");
+ if (DestLI.endIndex().isDead()) {
// A dead PHI's live range begins and ends at the start of the MBB, but
// the lowered copy, which will still be dead, needs to begin and end at
// the copy instruction.
bool isLiveOut = false;
for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
SE = opBlock.succ_end(); SI != SE; ++SI) {
- if (SrcLI.liveAt(LIS->getMBBStartIdx(*SI))) {
+ SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
+ VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
+
+ // Definitions by other PHIs are not truly live-in for our purposes.
+ if (VNI && VNI->def != startIdx) {
isLiveOut = true;
break;
}