using namespace llvm;
STATISTIC(NumAtomic, "Number of atomic phis lowered");
-STATISTIC(NumSplits, "Number of critical edges split on demand");
STATISTIC(NumReused, "Number of reused lowered phis");
char PHIElimination::ID = 0;
static RegisterPass<PHIElimination>
X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
-const PassInfo *const llvm::PHIEliminationID = &X;
+char &llvm::PHIEliminationID = PHIElimination::ID;
void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
// Create a new register for the incoming PHI arguments.
MachineFunction &MF = *MBB.getParent();
- const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
unsigned IncomingReg = 0;
bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
++NumReused;
DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi);
} else {
+ const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
}
- TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC,
- MPhi->getDebugLoc());
+ BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), DestReg)
+ .addReg(IncomingReg);
}
// Update live variable information if there is any.
// Insert the copy.
if (!reusedIncoming && IncomingReg)
- TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC,
- MPhi->getDebugLoc());
+ BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
// (not considering PHI nodes). If the register is live in to this block
// anyway, we would gain nothing from splitting.
if (!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB))
- SplitCriticalEdge(PreMBB, &MBB);
+ PreMBB->SplitCriticalEdge(&MBB, this);
}
}
return true;
}
-
-MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
- MachineBasicBlock *B) {
- assert(A && B && "Missing MBB end point");
-
- MachineFunction *MF = A->getParent();
-
- // We may need to update A's terminator, but we can't do that if AnalyzeBranch
- // fails. If A uses a jump table, we won't touch it.
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
- MachineBasicBlock *TBB = 0, *FBB = 0;
- SmallVector<MachineOperand, 4> Cond;
- if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
- return NULL;
-
- ++NumSplits;
-
- MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
- MF->insert(llvm::next(MachineFunction::iterator(A)), NMBB);
- DEBUG(dbgs() << "PHIElimination splitting critical edge:"
- " BB#" << A->getNumber()
- << " -- BB#" << NMBB->getNumber()
- << " -- BB#" << B->getNumber() << '\n');
-
- A->ReplaceUsesOfBlockWith(B, NMBB);
- A->updateTerminator();
-
- // Insert unconditional "jump B" instruction in NMBB if necessary.
- NMBB->addSuccessor(B);
- if (!NMBB->isLayoutSuccessor(B)) {
- Cond.clear();
- MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
- }
-
- // Fix PHI nodes in B so they refer to NMBB instead of A
- for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
- i != e && i->isPHI(); ++i)
- for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
- if (i->getOperand(ni+1).getMBB() == A)
- i->getOperand(ni+1).setMBB(NMBB);
-
- if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
- LV->addNewBlock(NMBB, A, B);
-
- if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
- MDT->addNewBlock(NMBB, A);
-
- return NMBB;
-}