#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
-#include <set>
#include <algorithm>
+#include <map>
using namespace llvm;
STATISTIC(NumAtomic, "Number of atomic phis lowered");
-//STATISTIC(NumSimple, "Number of simple phis lowered");
namespace {
- struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
+ class VISIBILITY_HIDDEN PNE : public MachineFunctionPass {
+ MachineRegisterInfo *MRI; // Machine register information
+
+ public:
static char ID; // Pass identification, replacement for typeid
PNE() : MachineFunctionPass((intptr_t)&ID) {}
- bool runOnMachineFunction(MachineFunction &Fn) {
- analyzePHINodes(Fn);
-
- bool Changed = false;
-
- // Eliminate PHI instructions by inserting copies into predecessor blocks.
- for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
- Changed |= EliminatePHINodes(Fn, *I);
-
- VRegPHIUseCount.clear();
- return Changed;
- }
-
+ virtual bool runOnMachineFunction(MachineFunction &Fn);
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<LiveVariables>();
+ AU.addPreservedID(MachineLoopInfoID);
+ AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
typedef std::map<BBVRegPair, unsigned> VRegPHIUse;
VRegPHIUse VRegPHIUseCount;
+
+ // Defs of PHI sources which are implicit_def.
+ SmallPtrSet<MachineInstr*, 4> ImpDefs;
};
char PNE::ID = 0;
const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
+bool PNE::runOnMachineFunction(MachineFunction &Fn) {
+ MRI = &Fn.getRegInfo();
+
+ analyzePHINodes(Fn);
+
+ bool Changed = false;
+
+ // Eliminate PHI instructions by inserting copies into predecessor blocks.
+ for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
+ Changed |= EliminatePHINodes(Fn, *I);
+
+ // Remove dead IMPLICIT_DEF instructions.
+ for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(),
+ E = ImpDefs.end(); I != E; ++I) {
+ MachineInstr *DefMI = *I;
+ unsigned DefReg = DefMI->getOperand(0).getReg();
+ if (MRI->use_begin(DefReg) == MRI->use_end())
+ DefMI->eraseFromParent();
+ }
+
+ ImpDefs.clear();
+ VRegPHIUseCount.clear();
+ return Changed;
+}
+
+
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
/// predecessor basic blocks.
///
return true;
}
-/// InstructionUsesRegister - Return true if the specified machine instr has a
-/// use of the specified register.
-static bool InstructionUsesRegister(MachineInstr *MI, unsigned SrcReg) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).isRegister() &&
- MI->getOperand(i).getReg() == SrcReg &&
- MI->getOperand(i).isUse())
- return true;
- return false;
+static bool isSourceDefinedByImplicitDef(MachineInstr *MPhi,
+ MachineRegisterInfo *MRI) {
+ for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
+ unsigned SrcReg = MPhi->getOperand(i).getReg();
+ MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+ if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
+ return false;
+ }
+ return true;
}
/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
MachineInstr *MPhi = MBB.remove(MBB.begin());
+ unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
unsigned DestReg = MPhi->getOperand(0).getReg();
// Create a new register for the incoming PHI arguments.
// after any remaining phi nodes) which copies the new incoming register
// into the phi node destination.
//
- const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
+ const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
+ if (isSourceDefinedByImplicitDef(MPhi, MRI))
+ // If all sources of a PHI node are implicit_def, just emit an implicit_def
+ // instead of a copy.
+ BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
+ else
+ TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
// Update live variable information if there is any...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
LV->removeVirtualRegistersKilled(MPhi);
// If the result is dead, update LV.
- if (LV->RegisterDefIsDead(MPhi, DestReg)) {
+ if (MPhi->registerDefIsDead(DestReg)) {
LV->addVirtualRegisterDead(DestReg, PHICopy);
LV->removeVirtualRegistersDead(MPhi);
}
-
- // Realize that the destination register is defined by the PHI copy now, not
- // the PHI itself.
- LV->getVarInfo(DestReg).DefInst = PHICopy;
LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
}
// Now loop over all of the incoming arguments, changing them to copy into
// the IncomingReg register in the corresponding predecessor basic block.
//
- std::set<MachineBasicBlock*> MBBsInsertedInto;
- for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
- unsigned SrcReg = MPhi->getOperand(i-1).getReg();
- assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
+ SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
+ for (int i = NumSrcs - 1; i >= 0; --i) {
+ unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
+ assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"Machine PHI Operands must all be virtual registers!");
+ // If source is defined by an implicit def, there is no need to insert
+ // a copy unless it's the only source.
+ MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+ if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+ ImpDefs.insert(DefMI);
+ continue;
+ }
+
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI.
- MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMBB();
+ MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
// Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the
// same basic block.
- if (!MBBsInsertedInto.insert(&opBlock).second)
+ if (!MBBsInsertedInto.insert(&opBlock))
continue; // If the copy has already been emitted, we're done.
- // Get an iterator pointing to the first terminator in the block (or end()).
- // This is the point where we can insert a copy if we'd like to.
- MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
+ // Find a safe location to insert the copy, this may be the first
+ // terminator in the block (or end()).
+ MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
// Insert the copy.
- RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
+ TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
// terminator instruction at the end of the block may also use the value.
// In this case, we should mark *it* as being the killing block, not the
// copy.
- bool FirstTerminatorUsesValue = false;
- if (I != opBlock.end()) {
- FirstTerminatorUsesValue = InstructionUsesRegister(I, SrcReg);
+ MachineBasicBlock::iterator KillInst = prior(InsertPos);
+ MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
+ if (Term != opBlock.end()) {
+ if (Term->readsRegister(SrcReg))
+ KillInst = Term;
// Check that no other terminators use values.
#ifndef NDEBUG
- for (MachineBasicBlock::iterator TI = next(I); TI != opBlock.end();
+ for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end();
++TI) {
- assert(!InstructionUsesRegister(TI, SrcReg) &&
+ assert(!TI->readsRegister(SrcReg) &&
"Terminator instructions cannot use virtual registers unless"
"they are the first terminator in a block!");
}
#endif
}
- MachineBasicBlock::iterator KillInst;
- if (!FirstTerminatorUsesValue)
- KillInst = prior(I);
- else
- KillInst = I;
-
// Finally, mark it killed.
LV->addVirtualRegisterKilled(SrcReg, KillInst);
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